Imagination launches RISC-V computer architecture course
The “RVfpga: Understanding Computer Architecture” course will incorporate a wide range of teaching materials and practical exercises that will teach students the key elements of processor architecture, including IP cores, modifying a RISC-V core and their microarchitectures.
Professor David Patterson, who shares the ACM A.M. Turing Award with John Hennessy for contributions to RISC, says; “RISC-V is transforming processor design and software/hardware co-design. RISC-V is an open architecture, which enables open-source hardware implementations. This new option means that software development can occur alongside hardware development, accelerating the design path. The RVfpga course enhances the understanding of not only RISC-V processors but also the RISC-V ecosystem and RISC-V SoCs. This course provides a deep understanding of an industrial-strength processor architecture and system of increasing popularity, which will prove useful to students throughout their academic and industry careers.”
The course was created with academic partners Associate Professor Sarah Harris, co-author of the “Digital Design & Computer Architecture” textbook, and Associate Professor Daniel Chaver. It features an instructor’s guide, a student manual, 10 hands-on experiments, test materials, sample exam questions, and the associated IP and software. The source files for the materials are provided. This approach gives a degree of flexibility for the course to be adapted or augmented.
Associate Professor Sarah Harris, says; “RISC-V improves on previous processor generations in every conceivable way, from power consumption to performance and even increased security. As another huge step forward in computer architecture it is important for students to understand RISC-V at a fundamental level.”
Robert Owen, Director Worldwide University Programme, Imagination, says, “RISC-V will pervade every computing level in the next five years. Its openness has enabled designers at all levels to get involved with processors without having to worry about licencing at the early stages of design. Up to now, academic activity has been focused on SoC design. This course is the first to provide the foundation of understanding of the components of the RISC-V “engine” and how they come together.”
Key dates:
3rd September 2020, 2.55pm PDT – Associate Professors Sarah Harris and Daniel Chaver will give a presentation on the course at the RISC-V Global Forum
8th October 2020 – The IUP will be hosting a webinar on the course
November 2020 – Release of the complete course in English, to be followed by Chinese, Spanish and Japanese
More information
https://events.linuxfoundation.org/riscv-global-forum/program/schedule/
https://event.on24.com/eventRegistration/
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