Imagination lets universities see source RTL for a “real” MIPS core
The offering is part the company’s Imagination University Programme (IUP) – MIPSfpga – as part of which participating university departments can get free and open access to a fully-validated, current generation MIPS CPU in a complete teaching package.
CPU architecture is generally taught as part of electronic engineering, computer science and computer engineering courses, and is based one (or more) of a small number of major CPU architectures. Until now, says Imagination, what’s been missing from all of these courses is access to real, un-obfuscated RTL code that will enable staff and students to study and explore a real CPU.
The MIPS architecture was originally developed at Stanford University in the early 1980s. It has been the teaching architecture of choice for decades because of its elegant true RISC design, described by Dr. David A. Patterson and Dr. John L. Hennessy in their book, ‘Computer Organization and Design’, now in its fifth edition.
Through MIPSfpga, Imagination is providing universities with a simplified version of its popular MIPS microAptiv CPU core which has been configured by an academic specifically for academic use. Many academics are already familiar with the microAptiv CPU, and it already has a broad ecosystem of support based on its use in numerous commercial products including the PIC32MZ microcontroller (MCU) from Microchip Technology.
The MIPS CPU is being offered as part of a complete free-to-download package for universities, together with a Getting Started Guide, teaching guide for professors, and examples designed to enable students to see how the CPU works and explore its capabilities. With the materials, students can develop a CPU and take it through debug, running on an FPGA platform. This CPU, the company adds, has all the features (MMU, cache controllers, debug interfaces, etc.) required to run a full blown operating system (e.g. Linux). This is contrast to other university programmes where the core is usually encrypted (i.e. a black box) and can only run a simple RTOS.
The MIPSfpga deliverables were developed by Dr. David Harris and Dr. Sarah Harris, professors who co-wrote the popular book, ‘Digital Design and Computer Architecture’, now in its second edition. Dr. David Harris configured the MIPS CPU at the heart of MIPSfpga, and Dr. Sarah Harris developed the teaching materials.
This MIPS CPU configuration is designed to run on a low-cost FPGA platform, with guides available for the Digilent Nexys4 platform with a Xilinx Artix-7 FPGA, and the Terasic DE2 platform with an Altera Cyclone FPGA.
MIPSfpga is already running in several academic institutions including Harvey Mudd College, Imperial College London, University College London (UCL), and the University of Nevada, Las Vegas (UNLV).
The MIPSfpga CPU and related materials are available for download from the Imagination University Programme website now for first phase users via an application process. Academics should visit https://community.imgtec.com/university to register for the IUP and learn more.
Phase two, starting in June, will require only a simple click-through agreement. Additional teaching materials are being developed and will be made available later this year. Imagination is working with Xilinx through its University Program to roll out MIPSfpga to universities worldwide.
Imagination; https://community.imgtec.com/university
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