Imagination’s ‘heterogeneous inside & out’ cores meet many-core needs

Imagination’s ‘heterogeneous inside & out’ cores meet many-core needs

New Products |
By Graham Prophet

Target applications include advanced driver assistance systems (ADAS) and autonomous vehicles, networking, drones, industrial automation, security, video analytics, machine learning, and others which increasingly rely on heterogeneous computing.


Today’s heterogeneous SoC designs, Imagination says, require a mix of high-performance CPU clusters and GPU or accelerator clusters all processing common datasets. The I6500 provides a highly scalable solution which can coherently implement optimized configurations of CPU cores within a cluster – this is what Imagination tags ‘Heterogeneous Inside’ – as well as a variety of configurations of CPU clusters and GPU or accelerator clusters on a chip depending on the requirements of the system (‘Heterogeneous Outside’).

following pages; further core details; and adoption by Mobileye for ADAS vision processing

The MIPS I6500 CPU is a 64-bit, multi-threaded, multi-core, multi-cluster CPU that is scalable from embedded to cloud. Features include:

– Heterogeneous Inside: In a single cluster, designers can optimize power consumption with the ability to configure each CPU with different combinations of threads, different cache sizes, different frequencies, and even different voltage levels.

– Heterogeneous Outside: The latest MIPS Coherence Manager with an AMBA ACE interface to popular ACE coherent fabric solutions such as those from Arteris and Netspeed lets designers mix on a chip configurations of processing clusters – including PowerVR GPUs or other accelerators – for high system efficiency.

– Simultaneous Multi-threading (SMT): Based on a superscalar dual issue design implemented across generations of MIPS CPUs, this feature enables execution of multiple instructions from multiple threads every clock cycle, providing higher utilization and CPU efficiency.

– Hardware virtualization (VZ): I6500 builds on the real time hardware virtualization capability pioneered in the MIPS I6400 core. Designers can save costs by safely and securely consolidating multiple CPU cores with a single core, save power where multiple cores are required, and dynamically and deterministically allocate CPU bandwidth per application.

– SMT + VZ: The combination of SMT with VZ in the I6500 offers “zero context switching” for applications requiring real-time response. This feature, alongside the provision of scratchpad memory, suits the I6500 for applications which require deterministic code execution.

– Ideal for compute intensive, data processing and networking applications: The I6500 is designed for high-performance/high-efficiency data transfers to localized compute resources with data scratchpad memories per CPU, and features for fast path message/data passing between threads and cores.

– OmniShield-ready: Imagination’s multi-domain security technology used across its processing families enables isolation of applications in trusted environments, providing a foundation for security by separation.


The I6500 is based on the mature MIPS ISA which is broadly supported in the development ecosystem by multiple vendors, with a choice of compilers, debuggers, operating systems, hypervisors and application software all optimized for the MIPS ISA.

ADAS vision application

Jim Nicholas, EVP MIPS Processor IP, Imagination, comments, “With the I6500 we are setting a new standard for scalable, heterogeneous many-core designs – and providing a highly differentiated solution for visionary companies that want to transform markets. One of these visionary companies is Mobileye, which is leading the way in ADAS and autonomous driving technologies….. ”


The I6500 CPU will be at the heart of heterogeneous coherent processing clusters in Mobileye’s next-generation EyeQ5 SoC, which is designed to act as the central computer performing sensor fusion for Fully Autonomous Driving (FAD) vehicles starting in 2020. The EyeQ5 will feature eight multi-threaded MIPS CPU cores coherently coupled with eighteen cores of Mobileye’s Vision Processors (VPs). The VPs provide exceptional computing power within extremely low power budgets by combining Mobileye’s broad range of algorithms for mono/multi-camera driver assistance/ autonomous systems, supported by its special vision accelerators and Imagination’s MIPS CPUs for ultra-efficient, real-time processing and control.


Elchanan Rushinek, SVP engineering, Mobileye, says: “Imagination’s multi-threaded MIPS CPUs have helped us achieve performance increases of more than 6x with each successive generation of EyeQ SoCs. Now with the EyeQ5 we are looking at an 8x increase. The combination of Mobileye’s VPs and MIPS CPUs enables us to provide unrivalled computing power on a single processor while maintaining a very low power budget, and the hardware virtualization capability in the I6500 CPUs provides a solid foundation for an open software platform with multiple operating systems.”


Imagination Technologies;



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