Imec and Renesas Electronics claim first multi-standard RF receiver in 28 nm CMOS
The 28 nm receiver is a linear software-defined radio (SDR) operating from 400 MHz up to 6 GHz and supporting reconfigurable RF channel bandwidths up to 100 MHz. Through novel design and architecture techniques, the receiver operates at a low standard supply of 0.9 V, while maintaining +5 dBm of out-of-band IIP3 and tolerating 0 dBm blockers. It achieves noise figures down to 1.8 dB, occupies an active area of 0.6 mm2, and consumes less than 40 mW.
The ADC is a 410 MS/s dynamic 11bit pipelined SAR ADC in 28 nm CMOS. It achieves a peak Signal-to-Noise Distortion Ratio (SNDR) of 59.8 dB at 410 MS/s with a power consumption of 2 mW. By combining novel digital calibration techniques with a new ADC architecture, an excellent energy efficiency was achieved. The ADC, including an on-chip calibration engine, occupies an active area of 0.11 mm2.
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