The INSITE program was started in 2009 and now has more than 10 participants with a focus on enabling design for chip process nodes at 7nm and beyond.

INSITE makes use of the knowledge gained in IMEC’s lithography and logic device scaling programs to help companies anticipate design parameters and options for next-generation systems and applications. Developers are now faced by a large number of potential design choices at 7nm including: the required number of lithography exposures, device architecture such as FinFETs or lateral nanowires, the local interconnect scheme, cell architecture and the metallization scheme.

“Optimizing advanced nanotechnology nodes is highly complex and it needs focused expertise to meet challenges in areas such as patterning and power,” said Simon Segars, CEO of ARM, in a statement issued by IMEC.

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