Imec, ASML show logic and DRAM built with High NA EUV lithography
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Belgian research lab imec has shown patterned structures obtained after exposure with a 0.55NA high numerical aperture EUV scanner
The study at the joint ASML-imec High NA EUV Lithography Lab in Veldhoven, the Netherlands shows the viability of high NA lithography for the next generation of chip manufacturing below 2nm. The high NA EUV lithography machines built by ASML in the Netherlands, starting with the TWINSCAN EXE:5000, can cost hundreds of millions of dollars and there is a continuing discussion on whether this can be cost effective.
The project showed random logic structures down to 9,5nm (19 nm pitch), random vias with 30nm center-to-center distance, 2D features at 22nm pitch, and a DRAM specific lay out at P32nm were printed after single exposure. This used materials and baseline processes that were optimized for High NA EUV in the imec Advanced Patterning Programme.
Prior to the exposures, imec prepared dedicated wafer stacks with advanced resists, underlayers and photomasks, and transferred High NA EUV baseline processes such as optical proximity correction (OPC), integrated patterning and etch techniques to the 0.55NA EUV scanner.
This confirms the readiness of the ecosystem to enable single exposure high resolution High NA EUV Lithography says imec. ASML has shipped two high NA EUV machines, and Intel recently discussed its progress with the technology.
imec has successfully patterned single exposure random logic structures with 9,5nm dense metal lines, corresponding to an 19nm pitch, achieving sub 20nm tip-to-tip dimensions. Random vias with a 30nm center-to-center distance showcased excellent pattern fidelity and critical dimension uniformity. Furthermore, 2D features at a P22nm pitch exhibited outstanding performance, highlighting the potential of High NA Lithography to enable 2D routing.
Beyond logic structures, imec successfully patterned, in a single exposure, designs that integrate the storage node landing pad with the bit line periphery for DRAM. This achievement underscores the potential of High NA technology to replace the need of several mask layers by 1 single exposure.
“The results showcase the unique potential for High NA EUV to enable single-print imaging of aggressively-scaled 2D features, improving design flexibility as well as reducing patterning cost and complexity. Looking ahead, we expect to provide valuable insights to our patterning ecosystem partners, supporting them in further maturing High NA EUV specific materials and equipment,” said Steven Scheer, senior vice president of compute technologies & systems / compute system scaling at imec.
Luc Van den hove, president and CEO of imec added “The results confirm the long-predicted resolution capability of High NA EUV lithography, targeting sub 20nm pitch metal layers in one single exposure. High NA EUV will therefore be highly instrumental to continue the dimensional scaling of logic and memory technologies, one of the key pillars to push the roadmaps deep into the ‘angstrom era. These early demonstrations were only possible thanks to the set-up of the joint ASML-imec lab allowing our partners to accelerate the introduction of High NA lithography into manufacturing.”.
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