The 3nm node will have minimum drawn geometries lines and spaces of about 10nm and indeed the full pitch for routing on the design is 21nm giving a half pitch of 10.5nm. The chip is intended to be made using both extreme ultraviolet and 193 immersion lithography technology and the design rules at various levels in the chip reflect this, the two parties said.
IMEC utilized a common industry 64-bit CPU for the design with a custom 3nm standard cell library.
Cadence tools used included the Innovus implementation system that makes use of massively parallel computation to for the physical implementation system to achieve power, performance and area (PPA) targets. The Genus synthesis tool provides RTL synthesis that addresses FinFET process node requirements.
For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions.
“As process dimensions reduce to the 3nm node, interconnect variation becomes much more significant,” said An Steegen, executive vice president for semiconductor technology and systems at IMEC, in a statement. “Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated.”
Chin-Chi Teng, corporate vice president at Cadence, said: “Expanding upon the work we did with IMEC in 2015 on the industry’s first 5nm tapeout, we are achieving new milestones together with this new 3nm tapeout, which can transform the future of mobile designs at advanced nodes.”
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