IMEC, Coventor model 10nm, 7nm processes
European research institute IMEC (Leuven, Belgium) has announced a joint development project with EDA tools vendor Coventor Inc. (Cary, North Carolina) to work on the modeling of next-generation manufacturing processes using Coventor’s SEMulator 3D software.
SEMulator 3D is a physical modeling tool based on a voxel (volume pixel) cubic grid that can be used to track the effects of successive processing steps. It can be used to model the entire process flow and determine likely optimizations or sources of failure for completed circuits.
However, at the leading edge the correlation between semiconductor manufacturing equipment settings and the effects produced are complex and the process steps, their cumulative effect on the final circuit and on yield also needs to be calibrated. So SEMulator 3D is also being correlated against real physical structures produced by IMEC at its wafer fab. This can be used to improve processing accuracy and for Coventor to optimize its virtual fabrication platform for emerging market requirements.
"SEMulator 3D is being used to do integration-level modeling," said David Fried, semiconductor chief technology officer of Coventor. "There can be 700 or 800 individual operations to make a FinFET or a vertical NAND structure. We want to be able to predict something that is physically accurate."
"At 0.25-micron we could get the transistors right and TCAD was about implants and yields. By 22nm the battleground has moved to whether we can build this stuff at all and whether can fabricate at high yields. It is made yet more complex because of multipatterning lithography schemes. SEMulator has been called TCAD for process integration."
At IMEC process and integration experts have connected IMEC’s own optical lithography simulations with Coventor’s SEMulator3D virtual fabrication platform to explore FinFET scaling to the 7nm node and to compare the process window marginalities in several dense SRAM designs using Spacer Assisted Quadruple Patterning and either multiple immersion or EUV patterning cut/keep solutions. Moreover, a Spacer-Assisted Quad Patterning scheme for 7nm dense interconnect was devised using SEMulator3D, and process window marginalities for an immersion based multiple block patterning solution were analyzed. Additional collaboration will focus on the predictive modeling of Directed Self-Assembly for advanced patterning.
Dan Mocuta, manager of logic and interconnect process integration at IMEC, commented: "It helps us find problems before we run wafers." Mocuta said that the research work, which has been running for six months, would be applied to both FinFET and SOI manufacturing schemes. It would also be used to model the inclusion of materials such as III-V compound semiconductors and graphene in the transistor channel.
SEMulator 3D only provides the physical model and that is challenging because at such extreme geometries some structures may be only a few atomic layers. Other software is then used to model electronic effects, which may themselves be affected by electronic band structure distortions brought about by quantum mechanical effects at material boundries.
An Steegen, senior vice president process technology at imec said: “A virtual fabrication platform enables us to tie together integrated processing before all of the individual processes are available. The SEMulator3D tool gives us the visibility and accuracy to do that, and an integrated platform to bring together all the various elements of advanced processing before moving on to actual silicon.”
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