IMEC makes spin-orbit torque MRAM on 300mm silicon

IMEC makes spin-orbit torque MRAM on 300mm silicon

Technology News |
By Peter Clarke

With an endurance of over 5×1010, 210ps switching speeds, and power consumption down tp 300pJ, the SOT-MRAM devices from the 300mm line achieve similar or better performance as lab devices.

SOT-MRAM promises high endurance combined with low-power, sub-ns switching speed, which provides the potential to overcome the limitations of spin-transfer torque MRAM (STT-MRAM). Up till now, SOT-MRAM devices have only been demonstrated in the lab, but with this new demonstration, Imec has now shown full-scale integration of SOT-MRAM device modules on 300mm wafers using CMOS-compatible processes.

The SOT-MRAM device has a magnetic tunnel junction where a thin dielectric layer is sandwiched between a magnetic fixed layer and a magnetic free layer. Writing to the memory is performed by switching the magnetisation of this free magnetic layer, by a current. In STT-MRAM, this current is injected perpendicularly into the magnetic tunnel junction, and the read and write operation is performed through the same path. In an SOT-MRAM device, on the contrary, switching of the free magnetic layer is done by injecting an in-plane current in an adjacent SOT layer – typically made of a heavy metal. Because of the current injection geometry, the read and write path are de-coupled, significantly improving the device endurance and read stability.

IMEC has compared SOT and STT switching behaviour on one and the same device, fabricated on 300mm wafers. While switching speed during STT-MRAM operation was limited to 5ns, reliable switching down to 210ps was demonstrated during SOT-MRAM operation. The SOT-MRAM devices show unlimited endurance (>5×1010) and operation power as low as 300pJ. In these devices, the magnetic tunnel junction consists of a SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetised stack, using beta-phase tungsten (W) for the SOT layer.

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