The CFET is a further development of the stacked gate all around (GAA) nanowire form of transistor but one in which either n- or p-type GAAs are stacked above the other type so that two transistors occupy the space of one and CMOS logic circuitry can be supported efficiently.
IMEC claims its proposed CFET can eventually outperform FinFETs and meet the N3 requirements for power and performance. Imec’s proposed flow consists of stacking an n-type vertical sheet on a p-type fin. This choice benefits from the potential for strain engineering the electron mobility in the bottom pFET. However, there remains a challenge of reducing the parasitic resistance of the deep vias. This can be achieved by introducing advanced Middle of Line (MOL) contacts using ruthenium, IMEC said.
Standard cell area is mainly dependent on the accessing the transistor terminals and so the benefit of CFETs is not so much based on the reduction in the active footprint but in the simplification of transistor terminal access, IMEC said. As a result it is possible to reduce standard cells to three routing tracks from the six used in contemporary FinFET libraries and or SRAM cells a similar area reduction is possible by using the transistor stacking to go from a T6 footprint to a T4 footprint.
“Given its excellent characteristics and scaling potential, the CFET device is an excellent contender for the new device architecture we need for nodes beyond N3, pushing the horizon for Moore’s Law farther out,” said Julien Ryckaert, distinguished member of the technical staff at IMEC, in a statement.
Next: Which session?
The research has been presented at the VLSI Technology Symposium, in session T13: FET performance and scaling. The research as performed in cooperation with equipment companies TEL Coventor and Lam Research and with semiconductor companies that are part of IMEC’s core research program; Globalfoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, Toshiba Memory, TSMC and Western Digital.
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