IMEC proposes ‘reconfigurable’ AI chips

Technology News | May 19, 2025

By Peter Clarke

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Luc Van den hove, CEO of research institute IMEC (Leuven, Begium), is calling for the semiconductor industry to adopt three-dimensional, reconfigurable AI chips, to cope with fast-changing AI software.

AI algorithm development is moving faster than the current strategy of developing dedicated ASICs to address specific bottlenecks in AI data flows and computation, according to Van den hove, in a statement seen by Reuters ahead of its publication.

IMEC’s annual technology forum opens in Antwerp, Belgium, on Tuesday and continues on Wednesday.

Dedicated integrated circuits can take a year or two to develop and spend six months being maufactured in a wafer fab.

“There is a huge inherent risk of stranded assets because by the time the AI hardware is finally ready, the fast-moving AI software community may have taken a different turn,” Reuters reports Van den Hove saying.

According to the description from Reuters what Van den Hove is proposing is a three-dimensional, programable array of AI computational processing elements.

Nvidia has grown to be the largest semiconductor company by offering multi-processing GPUs for AI that are sufficiently general to address the multiple types of AI algorithm as they have been developed. It has also been protected from competition by its CUDA parallel computing platform and programming model.

But even as it has done this Nvidia’s GPUs are not the most power efficient solution for specific algorithms. As a result, hyperscalers and others have been seeking to develop ASIC accelerators to address particular sets of workloads in the datacenter.

While larger companies may be able to afford this, it is risky and uneconomical for most companies, Van den hove said.

With the front line of AI moving from LLMs towards multi-mode agentic AI, the pace of algorithmic change could even be speeding up. The IMEC CEO is expected to propose that future AI chips group multiple AI compute styles within a building-block processing element – a so-called supercell. A programmable network-on-chip will then be able link and program resources to address algorithm requirements dynamically or at run time.

The approach will make use of three-dimensional stacking and other advanced packaging methods, Reuters said.

What Reuters is reminescent of field-programmable gate array but at a higher level of abstraction than the original gate-level look-up-table (LUT). The supercell, the building block in the array, will likely be composed of a variety of in-memory compute processing that attempts to support the full breadth of AI processing styles and requirements.

While the approach appears to make sense, it should be noted that if AI algorithms consistently turn away from some of the computation styles supported in the supercell of the component then the “FPGA of AI” could contain redundant silicon and become an expensive, but potentially still energy-efficient and performant solution. Balancing performance, power and area (PPA) continues to challenge chip designers and FPGAs have traditionally been selected for time-to-market benefits but at greater unit costs.

IMEC has been the world’s leading hub for semiconductor research for decades and works with the leading semiconductor companies in pre-competitive projects. This has allowed IMEC to propose and assess many of the technologies now being adopted at the leading-edge. These include FinFETs, gate-all-round transistors, backside power distribution, chiplets.