IMEC provides DRAM review, mulls R&D directions

IMEC provides DRAM review, mulls R&D directions

Technology News |
By Peter Clarke

The consideration of likely developments for DRAM comes at the conclusion of an ‘all-you-need-to-know’ history of DRAMs, from basic operation up to the more complex application-specific manifestations. The primer was written by Timon Evenblij, a system memory architect at IMEC and Gouri Sankar Kar, memory program director at IMEC.

The authors say IMEC is currently pursuing two research directions; one is to improve the dynamic nature of DRAM and the second is to replace the silicon transistor in the bit-cell, with a low-leakage, indium-gallium-zinc-oxide (IGZO) transistor.

The use of ferroelectric capacitors – rather than dielectric capacitors – could let DRAM cells retain charge for longer, with numerous benefits in simplification, power down modes and reduced power consumption. This is in engineering terms a relatively minor change but would still require a new DRAM architecture standard to fully exploit the capabilities, the authors observe.

However, longer-term benefits may come from a more radical change – dispensing with the silicon transistor in the DRAM bit cell – the authors argue.

This could be done by using a transistor made from low-leakage deposited semiconductor thin-film transistor (TFT), such as IGZO. The low-leakage allows the idea of the capacitor-less DRAM and because the silicon is no longer required for the DRAM area it allows the silicon peripheral circuitry to be moved under the array, saving area. More importantly avoiding the use of the substantial capacitor currently present in DRAM, opens up the possibility of stacked planes of DRAM arrays in the manner of 3D-NAND.

The authors concluded by saying IMEC is looking at potential multilayer DRAM circuits for a future high-performance DRAM standard that would allow scale up beyond currently assumed limits.

Related links and articles:

IMEC DRAM review

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