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IMEC reports nanowire FET in ‘vertical’ SRAM

Technology News |
By Peter Clarke


In particular the research institute has reported at the 2016 VLSI Symposium an SRAM circuit based on stacked junction-less vertical nanowire FETs to produce a smaller SRAM than would be possible with lateral transistors. 

In the paper IMEC has reported junction-less transistors built in both lateral and vertical configurations and are described as a promising candidate for logic, scaled SRAM cells, analog, and RF applications.

Although ICs are at present are predominantly lateral and semi-planar a movement towards vertical and 3D structures is predicted to take place because of limitations and costs of further 2D miniaturization via lithography. Considerable SRAM scaling is possible via the stacking of vertical devices, IMEC said.

Chip production moved to the FinFET – where the gate wraps around three-out of four sides of a silicon channel – some years ago. IMEC claims that wrapping the gate all the way round the device body for optimum electrostatics control is promising for enabling (sub-)5nm CMOS scaling. Junction-less devices have been also under research for some time because they eliminate some process steps (see Junctionless transistor could simplify chip making, say researchers).

At the VLSI Symposium 2016 IMEC has reported on control of nanowire doping versus nanowire size to optimize performance. Particular reference to raw performance for analog and RF applications and similar speeds and voltage gains are reported as those achieved by inversion-mode nanowire FETs, IMEC said. IMEC also reported on the variability of such parameters as transition voltage and demonstrated the construction of vertical nanowire junctionless FETs on the same 300mm-diameter wafers used for lateral silicon devices.

IMEC has proposed a novel SRAM cell design with two vertically stacked junction-less vertical nanowire FETs with the same channel doping, thus enabling reduction of the SRAM area per bit by 39 percent.

IMEC’s research into advanced logic is performed in cooperation with partners in its core CMOS programs including Globalfoundries, Intel, Micron, SK Hynix, Samsung, TSMC, Huawei, Qualcomm and Sony.

IMEC is clearly of the opinion that GAA nanowires could be adopted and demonstrate benefits almost immediately at 7nm although such changes are typically slow and may take several years. An Steegen, IMEC senior vice president of process technology is set to give a talk at Semicon West in July called “Pathfinding beyond 5nm”

Speaking at the IMEC Technology Forum held in Brussels recently Steegen pointed out that as FinFETs move from 10nm nominal to 7nm nominal the performance gains would be less than 30 percent in voltage scaling and less than 15 percent in clock frequency whereas a 7nm nanowire device should see  greater than 44 percent improvement in power consumption and greater than 20 percent improvement in performance. This gains are at a similar scale for the transition to 5nm as well, Steegen has indicated.

Related links and articles:

www.imec.be

vlsisymposium.org

News articles:

Intel taps junctionless transistor research

Junctionless transistor could simplify chip making, say researchers

IMEC starts quantum computing initiative


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