IMEC semiconductor roadmap shows end of metal-pitch scaling

IMEC semiconductor roadmap shows end of metal-pitch scaling

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By Peter Clarke

The IMEC research institute has published a roadmap graphic that shows semiconductor scaling continuing on from a nominal 2nm node to reach higher densities in 2036

However, the roadmap shows that while transistor and material innovations will continue in a nominal angstrom era, metal-pitch scaling will end at about 16nm to 12nm in 2030.

IMEC, the world’s leading independent research location for semiconductor manufacturing, points out that scaling of semiconductor technology will become even more complex. As such physical scaling of structures is only one factor and that, with cooperation, in terms of circuit density Moore’s Law can continue.

The roadmap contains many ideas that IMEC has already published but does discuss the idea of “context-aware interconnect” as a way to improve future circuit architectures.

The need to do this is great because of the vast and increasing amounts of data society is expected to generate, IMEC observes. The task is also difficult many parameters associated with scaling have hit limits.

IMEC calls these five walls that must be overcome simultaneously. As is often the case with multivariant problems progress on one axis often comes as the expense of progress along another.  

The five “walls” are:

  • lithography-enabled scaling;
  • memory bandwidth;
  • power delivery and cooling;
  • sustainability of chip manufacturing;
  • and cost

IMEC says the key to success will be the adoption of novel transistor structures novel circuit architectures and novel materials

IMEC semiconductor roadmap. Source: IMEC.

The move to high numerical aperture extreme ultraviolet lithography is also key and this is expected to come from ASML with the first prototype in 2023 and insertion into high-volume manufacturing in 2025 or 2026.

IMEC has already put a great deal of thought into what comes after the FinFET in terms of transistor structure (see Stacked CMOS could overcome Forksheet limitations, says IMEC and IMEC shows backside power delivery with buried power rails).

Some of its ideas such as nanosheet gate-all-around transistors are being adopted right now by the Intel, Samsung and TSMC at 3nm and 2nm (see Samsung to introduce nanosheet transistors in 3nm node, Intel renames manufacturing nodes, tips RibbonFET, PowerVia and IEDM: TSMC to report 2D nanosheet transistor)

The forksheet transistor is an imec invention, even denser than the nanosheet transistor, extending the gate-all-around concept to the 1 nm generation. The forksheet architecture introduces a barrier between the negative and positive channels, enabling the channels to come closer together. This architecture is expected to enable a cell-size shrink of 20 percent.

Forksheet then CFET

After the Forksheet transistor comes the complementary FET (CFET), which embodies some of the virtues of the CMOS architecture within a vertical successor to the GAA. This improves circuit density but at the cost of process complexity. It is with the introduction of the CFET that industry may be ready to deploy 2D monolayer materials such as tungsten disulphide or molybdenum disulphide. These should bring improved performance and reduced power consumption.

Meanwhile IMEC has previously introduced the idea of using buried power rails to distribute power around an IC rather competing for real-estate with signal wires on top of an IC. Power rails will sink into the wafer and be connected to the backside using nano-through-silicon vias in wider, less resistive materials.

Classical Von Neumann architectures that separate memory from processing unit have clearly become inefficient at scaling. “We’ll need to evolve toward domain-specific and application-dependent architectures, with massive parallelization comparable to the way our human brain works. This implies that the CPU will have a smaller role in favor of custom-made circuits for specific workloads,” said IMEC. But they are also describing the AI and machine learning circuits that are being deployed in datacenters and at the edge.

Related links and articles:

News articles:

Here comes the forksheet transistor, says IMEC

Samsung to introduce nanosheet transistors in 3nm node

Intel renames manufacturing nodes, tips RibbonFET, PowerVia

IEDM: TSMC to report 2D nanosheet transistor

IMEC shows backside power delivery with buried power rails


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