imec shows backside power delivery with buried power rails
Belgian research lab imec is making the first experimental demonstration of a routing scheme for logic chips with backside power delivery using nano-through-silicon-vias (nTSVs) landing on buried power rails (BPRs).
This is a key technology for future 2.5D and 3D chips built on 2nm process technology and shown at the 2022 IEEE VLSI Symposium on Technology and Circuits in the US this week.
The BPRs connect to scaled FinFET devices whose performance was not impacted by backside wafer processing. This also offers a system performance benefit by improving the power delivery and a performance boost by adding capacitors on the back of the wafer.
Backside power delivery allows to decouple the power delivery network from the signaling metallization scheme in logic chips, reducing the routing congestion. Since imec’s first announcement in 2019, different implementations have been proposed. At VLSI 2021 imec for the first time showed backside connectivity through nTSVs landing on metal-1 pads in the wafer’s frontside.
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“We believe that combining backside power delivery with buried power rails – a structural scaling booster in the form of a local power rail that is buried deep in the chip’s front-end-of-line – is the most promising implementation scheme of a backside power delivery network in terms of scalability and performance,” said Naoto Horiguchi, Director CMOS Device Technology at imec.
“With our test vehicle, in which nTSVs land on buried power rails defined in the wafer’s frontside, we show that the performance of the FinFETs is not degraded by backside processing,” he said. “This includes bonding of the wafer to a carrier wafer, wafer backside thinning and processing of ~320nm deep nTSVs. The nTSVs land on BPRs with tight overlay control and are implemented at a tight pitch of 200nm without consuming any area of the standard cell. This ensures further scalability of the technology towards 2nm and beyond.”
“In a 2022 VLSI paper by R. Chen et al., we combined backside processing with the implementation of a 2.5D (i.e., pillar-like) metal-insulator-metal capacitor (MIMCAP), which serves as a decoupling capacitor,” said Eric Beyne, VP R&D of imec’s 3D System Integration. “The 2.5D MIMCAP boosts capacitance density with a factor of 4 to 5x, allowing a further improvement of the IR drop (32.1%/23.5% over the no-MIMCAP/2D-MIMCAP counterparts, respectively). The results are derived from an IR drop modelling framework calibrated with experimental data.”
“Our work shows that the backside can create a very dynamic design space with new design options that can help address shortcomings of traditional 2D IC scaling,” said Beyne. “In addition, we have shown its validity for 3D system scaling technologies, where the carrier wafer in de bonding process is replaced with a functional wafer with a logic wafer for enabling logic-on-logic 3D-SOCs, and the bottom dies are powered from the backside.”
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