imec shows working CFET devices for next gen 0.7nm chip designs

imec shows working CFET devices for next gen 0.7nm chip designs

Technology News |
By Nick Flaherty

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Belgian research lab imec has demonstrated the first electrically functional CMOS complementary FET (CFET) devices with stacked bottom and top source/drain contacts.

CFET devices are a key contender for next generation process technologies below 1nm. These are two transistors tacked on top of each other, each with a 18nm gate length, 60nm gate pitch and 50nm vertical separation between n and p devices. Electrical functionality was demonstrated on a test vehicle with nFET and pFET devices using a common gate, and top and bottom contacts connected from the frontside.

The CFET devices were built with both contacts patterned from the frontside, but imec has also shown the feasibility of moving bottom contact formation to the back side of the wafer wafe. This significantly improves the top device survival rate from 11% to 79%, and builds on key work that imec has been doing with Intel, TSMC and ARM.

The imec roadmap predicts the use of CFET devices in the A7 (0.7nm) node device architectures and follows the first description of CFETs back in 2018.  

imec looks to process flow for sub-nm stacked CFET transistors

However the transistor design is not the only issue for sub-1nm process technologies. Advanced metal routing techniques, including bringing in power and signals from the back of the wafer that than the top, can reduce standard cell track heights by 20% without reducing the performance.

Backside power key to Intel process

The functional CFET devices were described at the 2024 VLSI Symposium where the proposed process flow includes two CFET-specific modules: the middle-dielectric isolation (MDI), and the stacked bottom and top contacts.

MDI is a module pioneered by imec to isolate top and bottom gate and differentiate on the threshold voltage settings between n and p devices. The MDI module is based on modifying the CFET ‘active’ multi-layer Si/SiGe stack and allows the co-integration of the inner spacer, a nanosheet-specific feature that isolates the gate from the source/drain.

“We obtained the best results in terms of process control with an MDI-first approach,” said Naoto Horiguchi, Director CMOS device technology at imec. “Before source/drain recess, the step where nanosheets and MDI are ‘cleaved’ to gain access to the channel sidewalls and start source/drain epi. An innovative source/drain recess etch with ‘in-situ capping’ enables MDI-first by protecting the gate hardmask/gate spacer during the source/drain recess.”

A second critical module is the formation of stacked source/drain bottom and top contacts, vertically separated by dielectric isolation. Key steps are the bottom contact metal fill and etch back, and subsequent dielectric fill and etch back – all within the same tight space as available for the MDI stack.

“When developing the bottom contacts from the frontside, we encountered multiple challenges, affecting bottom contact resistance and limiting the process window for top device source/drain formation,” said Horiguchi.

“At 2024 VLSI, we show that it is feasible to move the bottom contact formation to the wafer backside, despite additional process steps linked to wafer bonding and thinning. The top device survival rate increased from 11% to 79%, making backside bottom contact formation an attractive option for industry. Research is currently ongoing to identify the optimal contact routing approach.”

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