Imec solves metallization issues in advanced interconnects for the sub-1X technology node
The process is said to provide excellent adhesion, film conformality, intrinsic barrier property and reduced line resistance. This technology paves the way towards interconnect Cu metallization into the 7nm node and beyond.
With continuous interconnect scaling, the wire resistance per unit length increases, which has a detrimental impact on the device performance (RC). Moreover, when reducing the dimensions with conventional barrier layers, an increased loss of copper (Cu) cross sectional area is observed, resulting in high resistance and decreased interconnect lifetime (electro-migration and time dependent dielectric breakdown – EM and TDDB).
To overcome these interconnect metallization issues when scaling beyond the 1X technology node, imec’s R&D program on advanced interconnect technology explores new barrier and seed materials as well as novel deposition and filling techniques. The Mn-based SFB was demonstrated to be an attractive candidate for future interconnect technology. At module level, Mn-based SFB resulted in a 40% increase in RC benefits at 40nm half pitch compared to conventional barrier and good lifetime performance (comparable to TaN/Ta reference).
These results were achieved in cooperation with imec’s key partners in its core CMOS programs Globalfoundries, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, SK hynix, Fujitsu and Sony.
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