imec taps CCD for 3D CXL memory in data centres
Belgian research lab imec has developed a 3D charge-coupled device that could be used as a replacement for DRAM in data-intensive compute applications.
The compute express link (CXL) type-3 buffer memory promises to vastly surpass DRAM in terms of bit density and cost efficiency. This buffer memory is a off-chip pool of memories
that feeds the various processor cores with large data blocks via a high-bandwidth CXL switch.
The design, shown at the 2024 IEEE International Electron Devices Meeting (IEDM) in San Francisco this week, uses 3D integrated charge-coupled device (CCD) technology adopted from image sensors combined with an oxide semiconductor channel material such as indium gallium zinc oxide (IGZO). This could provide five times the density of existing DRAM buffers.
(Top) Schematic illustrating the IGZO-based planar CCD structure, and (bottom) cross-sectional TEM image showing a series of gates, with the zoom-in detailing the distinct layers.
imec has developed a planar 2D proof-of-concept CCD structure as a block-addressable buffer memory which can store 142 bits and is working on a 3D version with multiple layers.
The IGZO channel ensures sufficiently long retention time and enables 3D integration in a cost-efficient, 3D NAND-like architecture, and imec expects the 3D CCD memory density to scale far beyond the limits of DRAM scaling.
The CXL) memory interface provides opportunities for new memories to complement DRAM in
data-intensive compute applications such as AI. The type 3 buffer has different specifications than byte-addressable DRAM, allowing other structures with block addressability, unlimited endurance, low fabrication cost, and sufficient data retention.
The planar CCD structure of this 2D proof-of-concept consists of an input stage, 142 stages (each consisting of four phase gates) which can each store one bit, and a two-transistor-based read-out stage.
The CCD register is written by injecting charges through the input stage and sequentially transferring them through all 142 stages by switching the voltages of the phase gates. The CCD offers more than 200s retention, an endurance of >1010 cycles without degradation, and a charge transfer speed exceeding 6MHz.
Multilevel storage capability of the CCD register was also demonstrated, contributing to a higher bit density suitable for a CXL memory buffer.
Estimated bit density vs. number of layers of the proposed 3D CCD memory, assuming 2 bits/cell, 30% array overhead and 3-phase clock operation.
“The real value of the proposed buffer memory lies in its ability to be integrated into 3D NAND fashion, with IGZO-based CCD registers integrated into vertically aligned plugs – a concept that we now propose for the first time,” said Maarten Rosmeulen, Program Director Storage Memory at imec. “From what is possible with NAND flash today with the capability of processing 230 layers, we estimate that our 3D buffer memory can already provide five times more bit density than what (2D) DRAM is expected to offer in 2030. We are currently investigating real 3D implementations with limited number of word lines.”
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