IMEC, Unisantis develop vertical-transistor SRAM

IMEC, Unisantis develop vertical-transistor SRAM

Technology News |
By Peter Clarke

The two organizations are working on an extreme ultraviolet lithography enabled process to produce a six-transistor SRAM cell with an area of about 0.02 square microns. This would meet or exceed the cell area of the N5 (5nm) technology node but because the transistors are organized vertically with gate all around a pillar would have a much-relaxed pitch of about 50nm

An Steegen, executive vice president of semiconductor technology and systems, said that the vertical gate-all-around SGT-based cells have a 20 to 30 percent reduced area compared to horizontal gate-all-around FETs, while also outperforming these in terms of operating voltage, standby leakage and stability.

“SGTs have all the advantages of horizontal gate-all-around transistors, allowing a near-perfect electrostatic control of the transistor channel,” says Professor Masuoka, in a statement issued by IMEC. “But because the channel is a vertical pillar, the concept has the potential for a significant area reduction compared to horizontal nanowire-based transistors.”

Unisantis is not so much a startup as long-term research team. It was founded in 2004 to develop three dimensional transistors and was joined by Professor Fujio Masuoka as chief technology officer. Previously Professor Masuoka had spent 23 years at Toshiba Corp. He is credited as the inventor of the flash memory. Since 2007 Unisantis has been working with the Institute of Microelectronics in Singapore on the development of Surrounding Gate Transistors.

IMEC and Unisantis used design process technology co-optimization (DCTO) to develop both the SRAM design with a bit-cell area of 0.0205 square microns, using a minimum pillar pitch
of 50nm. This is 24 percent better than the smallest SRAM designs published to date.

Next: EUV plays its part

One key challenge of the development involved the mechanical stability of the pillars at the high aspect ratios required. Through the use of single-exposure EUV lithography – rather than quad exposure optical immersion lithography the number of process steps was reduced. This improved mechanical stability and resulted in cost comparable to that of a FinFET-based SRAM.

Steegen said that IMEC and Unistantis have designed individual bit cells and small arrays of various sizes. The circuits are in the process of being fabricated and Steegen said she expected electrical results soon.

In a side meeting at the ITF Steegen was asked whether the SGT would be applicable to general logic as well as to SRAMs. Steegen said yes in principle but pointed out that for general logic IMEC generally reckoned on using three lateral wires in a gate-all-around extension of a FinFET. Therefore, it would be logical that three vertical transisitors would be required. This would reduced the area advantage that is present in the SRAM case.

Unisantis has not been explicit about its business model but has said that foundries could manufacture devices with current tooling suggesting the company might be looking to pursue a licensing approach to the market.

Steegen said IMEC has a collaboration agreement with Unisantis to produce devices. “Then we will see what the next steps will be.”

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