Imperas details verification of automotive AI RISC-V vector processor IP
Imperas Software in the UK and Cadence Design Systems have detailed the verificaiton flow for NSITEXE developing an automotive AI RISC-V processor core.
The two worked on a comprehensive verification flow for the NSITEXE Akaria processor IP, including the NS72, which is an out-of-order 64-bit RISC-V processor with the RVV vector extensions. This is aimed at automotive AI chips and other safety critical embedded designs for parent company Denso.
The ImperasDV RISC-V processor verification tools are used with the Cadence verification flow, including the Xcelium Logic Simulator and Verisium Artificial Intelligence (AI)-Driven Platform for debug, analysis and management.
ImperasDV is a RISC-V processor verification solution based on the industry-leading lock-step continuous compare methodology. It enables both accurate detection of issues and the efficient resolution of discrepancies between the design under test and the Imperas RISC-V Reference Model.
The Cadence Xcelium Logic Simulator provides the SystemVerilog simulation environment, including the tightly-integrated, high-performance interface required to work with ImperasDV effectively. These are used with the Cadence SimVision Debug and analysis tools to create a unified environment RISC-V, with its open-standard Instruction Set Architecture (ISA), offers processor developers many options and configurable features, enabling the development of optimized domain-specific processors.
ImperasDV supports the RISC-V design verification tasks across the complete specification, plus custom instructions, with the Imperas RISC-V reference model, architectural validation tests, additional functional test suites, coverage analysis, and simulation-based test methodologies for asynchronous events and debug operations.
“The NSITEXE Akaria processors, developed with the use of Imperas RISC-V verification technology and the leading-edge SystemVerilog simulator and debug tools from Cadence, are targeted to address the high-performance requirements for AI and automotive requirements. The Akaria processors include the necessary features and quality to achieve the ISO 26262 ASIL D functional safety standard, in addition to being optimized and efficient processors for the next-generation embedded applications,” said Hideki Sugimoto, CTO of NSITEXE, Inc., a group company of DENSO Corporation.
“As the NSITEXE Akaria processors are adopted across a wide range of next-generation automotive, safety-critical, and embedded applications, the verification methodology with the support from Imperas and Cadence has been invaluable in achieving our quality goals and on-time development schedule.”
“By integrating our Xcelium Logic Simulator with Imperas’s RISC-V verification technology, we’ve empowered NSITEXE to design the next-generation of its Akaria processors, which are optimized for safety-critical applications and compliant with the ISO 26262 ASIL D standard,” said Paul Cunningham, general manager of the System & Verification Group at Cadence. “Our work together exemplifies Cadence’s commitment to collaboration and innovation to support our customers in the rapidly evolving semiconductor industry.”
“Processor verification is challenging, and yet critical to RISC-V adoption,” said Simon Davidmann, CEO at Imperas Software Ltd. “ImperasDV is the first commercially available RISC-V processor verification solution, and the achievement of the tight integration with Cadence is key to the successful use of ImperasDV by NSITEXE.”
Cadence, Imperas, and NSITEXE have released more detail on the design flow and implementation of the lock-step continuous compare RISC-V verification methodology as a case study. This describes the NSITEXE RISC-V processor IP, including the verification challenges of the NS72 architecture, the lock-step continuous compare verification methodology being used for processor DV, and examples of bugs that were avoided by using this method. The case study describes the integration between Imperas and Cadence tools used and details of the full verification flow.
The case study is available now at https://www.imperas.com/docs.
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