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Imperas launches RISC-V Physical Memory Protection (PMP) validation test suite

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By Nick Flaherty

Imperas Software has launched a beta version of its architectural validation test suites for RISC-V Physical Memory Protection (PMP).

PMP is a key requirement for making embedded chips more secure, and the open standard Instruction Set Architecture (ISA) of RISC-V offers developers a wide range of standard extensions and options for optimized processors.

The RISC-V Privileged Specification includes PMP as a fundamental approach to memory protection that is essential in security applications that depend on TEE (Trusted Execution Environments) such as Keystone, OpenTitan, and many other leading techniques for security protection. This means functional verification of PMP is essential for any RISC-V processor targeted at security applications.

RISC-V processor implementations for security applications use physical memory protection (PMP) as a way to ensure memory isolation between key security applications and other activities and the specification provides a flexible and comprehensive approach based on control registers for the parameterization of modes to control the memory access, permissions, and policy. By using control registers, the actual policy and operation can be configured in software using the available hardware resources and the PMP policy can be configured to control the initial processor boot process. This is fundamental to many systems that rely on a TEE for security applications.

However RISC-V processor functional verification needs to ensure the design behaves as expected. In the case of the PMP functionality, due to the wide range of possible configurations and implementations, the architectural validation test suite also needs to cover the vulnerabilities that arise from a design error that enable an unnecessary or unwanted option.

While some processor developers undertake both the design and test phases of a project, the advantage that 3rd party tests provide is an independent interpretation of the specification and thus offer a valuable additional safeguard. This is especially important when specification options selected for the target device are used to direct the test plan, since an unintended design error that includes an unnecessary and therefore untested feature could allow for a security vulnerability.

“A key part of the RISC-V privilege specification that is fundamental for OS and application security is the PMP feature,” said Allen Baum of Esperanto Technologies and Chair of the RISC-V International Architecture Test SIG. “Enabling its correct operation is essential for security applications, and the Imperas PMP test suites are a valuable contribution to the RISC-V compatibility and verification community.”

 “In any verification plan, the opportunity to use more tests is always a useful option, but as is often the case some tests are more useful than others,” said Simon Davidmann, CEO at Imperas Software. “Test suites have many useful qualities, perhaps the top two are coverage and specification completeness. The RISC-V PMP test requirements are significant given the complexity of the specification and security implications for any implementation errors. The Imperas mutating fault simulation technology ensures the test coverage, and the Imperas reference model covers the full envelope of the PMP specification, so when combined these produce a useful architectural validation test suite for any RISC-V processor targeted at security applications.”

The Imperas Physical Memory Protection (PMP) Architectural Validation test suites are available now to ImperasDV users as a beta release, with a full production release scheduled for Q2 2022.

The ImperasDV RISC-V processor verification technology is already in active use with many leading customers, some of which have working silicon prototypes and are now working on second generation designs. These include Codasip, EM Microelectronics (Swatch), NSITEXE (Denso), Nvidia Networking (Mellanox), the OpenHW Group, MIPS Technology, Seagate Technology, Silicon Labs, and Valtrix Systems.

The free riscvOVPsimPlus package, including the Imperas RISC-V Reference Model, test suites and instruction coverage analysis, including updates for the latest RISC-V ratified specifications is also available on OVPworld at www.ovpworld.org/riscvOVPsimPlus.

ImperasDV is available now, more details are available at Imperas.com/ImperasDV.

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