Imperas offers RISC-V processor models

Imperas offers RISC-V processor models

Technology News |
By Peter Clarke

Imperas is set to demonstrate these tools that support the development of embedded software at the RISC-V workshop in Shanghai, China, May 8 to 11 and at the Design Automation Conference in Austin, Texas, June 18 to 22.

Imperas has developed and released open source models of the RISC-V RV32I/RV32G and RV64I/RV64G cores through the Open Virtual Platforms website. These RISC-V models, together with other OVP models, APIs and the OVPsim virtual platform simulator, enable the building and customization of instruction accurate models and platforms for custom SoC subsystems, full SoCs, or larger systems for software development.

In China Imperas will demonstrate software debug on a RISC-V virtual platformand present a paper entitled: Modern Software Development Methodology.

“Imperas believes that the customizable, open RISC-V architecture is a boon to the embedded electronics industry, and that delivering our next-generation models, virtual platforms and software development methodology will help accelerate its adoption.” said Simon Davidmann, president and CEO of Imperas.

The addition of RISC-V models expands existing Imperas and Open Virtual Platforms (OVP) platform support to over 170 processor models across a wide variety of vendors.

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Imperas opens MIPS Warrior processor models

RISC-V Foundation clarifies ‘100 errors’ reports

Princeton finds bugs in RISC-V architecture

Codescape tools provide MIPS software life-cycle development environment

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