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Imperas opens MIPS Warrior processor models

Imperas opens MIPS Warrior processor models

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By eeNews Europe



The processor core models and example platforms are available from the Open Virtual Platforms website, www.OVPworld.org/MIPS.
The models of the P5600 and M51xx processor cores, as well as models of other MIPS processors, work with the Imperas and OVP simulators, including the QuantumLeap parallel simulation accelerator, performing at hundreds of millions of instructions per second.

All OVP processor models are instruction accurate, and very fast, focused on enabling embedded software engineers to have a development environment available early to accelerate the entire product development cycle.

Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the native TLM-2.0 interface available with all OVP processor models.

The OVP models also work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for hardware-dependent software development such as OS and CPU-aware tracing (instruction, function, task, event), profiling, code coverage and memory analysis.

The tools use the Imperas SlipStreamer patent pending binary interception technology. SlipStreamer enables these analytical tools to operate without any modification or instrumentation of the software source code, i.e., the tools are completely non-intrusive.

Visit Imperas at www.imperas.com

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