Imperas teams for system level verification for RISC-V

Imperas teams for system level verification for RISC-V

Business news |
By Nick Flaherty

Imperas Software in the UK has teamed up with Breker Verification Systems for system level verification of RISC-V designs.

Breker provides advanced test content synthesis for system on chip (SoC), UVM and Post-Silicon verification environments.

Imperas and Breker plan to develop interfaces and standards to unify the functional verification design flows to enable DV teams to improve efficiency and verification IP reuse across the complete verification process from plan to silicon prototype.

This will enable development teams to efficiently move from RISC-V processor functional design verification (DV) right through to system level and SoC integration testing, including automated cache coherency validation.

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The flexibility of the open, standard Instruction Set Architecture of RISC-V, SoC developers can now optimize a custom processor for domain specific applications. However, the use of these new RISC-V cores introduces additional system level integration verification challenges.

“RISC-V represents an inflection point for semiconductor verification as the design freedoms provided by the open ISA means an assumption of the responsibility of the processor and system verification task,” said David Kelf, CEO at Breker Verification Systems. “In partnering with Imperas, the leaders in RISC-V processor verification, we can offer a combination of technologies and interface standards for IP and SoC testing that ensures commercial-grade verification for these flexible devices right through to the end platform.”

“RISC-V marks the end of the one-size-fits-all approach to processor IP, now all SoC developers can explore new innovations with processor IP configured for the target application,” said Simon Davidmann, CEO at Imperas Software Ltd. “Many of our customers are exploring the design side possibilities of new processor architectures and their implications for SoCs and systems in parallel, extending the verification scope from IP cores to system level integration. With Breker’s proven system verification experience, we are streamlining the critical verification tasks to enable the full potential of RISC-V based devices with commercial-grade verified quality.”; 

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