Implementing analog functions in rugged, rad-hard FPGAs

Implementing analog functions in rugged, rad-hard FPGAs

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By eeNews Europe

FPGAs have already changed the cost/reliability paradigm for embedded systems in high-reliability applications, thanks to advances in hardness and power reduction. But on many embedded applications for high-reliability markets, designers depend on a number of peripheral analog components such as analog-to-digital and digital-to-analog converters to talk to the real world. Other system components such as phase-locked loops (PLLs) and DC/DC converters are usually required to complete a system design. These peripherals impact overall cost, size and reliability. Peripheral analog parts can also be challenging to work with and to source for radiation environments, as an example.

To further leverage the power of FPGAs, military-and-aerospace engineers are actively looking for ways to integrate many of these analog functions onto the FPGA. Synthesizable, digital IP cores that replace some analog functions now exist, allowing mil/aero designers to implement ADC, DAC, DC/DC controller and clock-multiplier functions in fully digital processes such as FPGAs. Not only does this new ability leverage the advantages of FPGAs, it also helps mitigate many challenges of using analog components in high-reliability applications.

Overcoming high-reliability design challenges

The engineering challenges of designing for military or high-reliability applications such as aerospace are numerous. Power and weight are usually under strict budgets because they can affect operating costs and insertion costs exponentially. Physical shock safeguards, force survival and protection from single-event upsets (SEUs) and latchup often mean that parts are larger, heavier and more power hungry than commercial devices. For instance, a commercial 12-bit, 10-MHz bandwidth ADC measures approximately .71 by .42 inches and consumes 280 milliwatts. The equivalent radiation-hardened part is .81 by .72 inches and consumes 335 mW. That’s almost double the size at 20 percent more power.

A wide temperature range is another issue. Typically, temperatures of -40°C to +80°C are expected for many military embedded applications here on Earth. Temperature takes on another complexion in space. In satellite electronics design, for instance, the normal operating junction temperature might be -55°C to +125°C. Monitoring this onboard temperature is key to effective system maintenance, but installing a rad-hard ADC part to provide this function can add up to one square inch of board and require additional components and testing.

When a high-reliability design makes use of peripherals such as ADCs, DACs, DC/DC converters or PLLs, each one of those components represents a possible point of failure. Each must be qualified and tested, and each is most likely not optimally designed for the specific need. There is also always a risk that the manufacturer will discontinue the part, forcing requalification of the entire system.

These challenges to working with analog components in high-reliability environments can evaporate by using the FPGA for a unified, all-digital approach. Let’s take a look at this new paradigm in military/aerospace design.

Pulling analog functions onto the FPGA

Regardless of how you define “analog” and “digital,” significant differences and integration issues exist between the two. Because of these issues, it can be very advantageous to have digital designers pull analog functions onto an FPGA and test them. Herein, we will define “digital” as using standard digital library cells and passive components for a fully synthesizable and digitally testable design. Designers can create digital IP blocks of ADCs, DACs, DC/DC converter controllers and clock multipliers in RTL format and implement them in all-digital processes.

With these IP blocks, military designers can take advantage of rugged and radiation-hardened FPGAs to implement customized analog functions. Not only does this approach leverage the inherent protection properties of the FPGA, but these blocks are also a great way to utilize unused FPGA resources. Xilinx recognizes this advantage and now partners with Stellamar to provide these functions. Increasingly, aerospace companies are turning to these solutions to attack analog-integration problems.

Digital ADC core yields benefits

Figure 1 depicts an example block diagram of a Stellamar Digital ADC IP core. With the digital approach, the core requires only a few external passive components. The IP core is instantiated right inside the FPGA and is easy to implement through digital synthesis. On a Xilinx Virtex-5QV device, a scenario such as that pictured in Figure 1 utilizes less than 1 percent of FPGA resources.

Figure 1: An example of a fully digital ADC IP core interface

Proprietary signal processing makes it possible to replicate analog sigma-delta ADC performance with all-digital library cells. Companies like SEAKR Engineering and the Finnish Meteorological Institute are using Digital ADC IP in their On Board Processor Program and Lunar Landing Missions, respectively. Some benefits are:

•  50 percent lower power than analog ADC parts
•  68 percent smaller area than analog ADC parts
•  Process technology independence
•  Reduced risk and cycle time
•  Digital integration, synthesis and testing
•  Easier radiation-hardened design

Performance plus applications

Current performance is up to 15 bits of resolution and several hundred kilohertz of bandwidth. Bandwidth depends on the selected resolution. This level of performance is suitable for a host of applications including sensors (temperature, pressure, voltage, current and acceleration), touchscreen integration, high-quality voice and motor control.

As an example, many design teams use a radiation-hardened, 12-bit, 10-MHz bandwidth ADC part for monitoring onboard temperature and voltage. Some FPGAs, such as the Xilinx Virtex-5QV space-grade FPGA, even have embedded diodes highlighting the importance of the temperature-sensing function. However, normal bandwidths for these types of measurements are 0.5 Hz to 10 Hz, so using bandwidth in the megahertz is like driving the head of a pin with a sledgehammer. A Digital ADC IP core on a radiation-hardened FPGA can get down to 0.5-Hz bandwidth per channel and can consume less than 6 mW, compared with 335 mW for the external part. Why waste critical board space and power for such a low-level task?

Controlling DC/DC power management

Power management is becoming a larger part of overall system design. Sometimes a single design can include more than 30 power supplies. External radiation-hardened DC/DC converters retain the same difficulties as external ADCs. Thus, the use of these parts to control power complexity in high-reliability applications does not scale well.

All-digital DC/DC controller IP now exists to take advantage of radiation-hardened FPGAs’ processes and to allow for simplification of control, redundant power supplies, infinite sequencing and infinite throttling (see Figure 2). You will still need an external power transistor, but this can be much easier to work with than a full DC/DC converter part.

Figure 2: Example DC/DC controller block diagram

Digital clocking solutions

Phase-locked loops are some of the most widely used analog blocks for clock generation; thus, most FPGAs have incorporated PLL capability within the package. However, some FPGAs, including certain radiation-hardened FPGA families, do not include PLLs at all. Other radiation-hardened FPGAs generally do not include the PLLs in the rad-hard portion of the package.

Digital clock multiplier IP used on these FPGAs can provide the ability to generate any clock up to about 2 GHz with no lock time. Models show 50-picosecond peak and 35-ps RMS, with 5-ns to 1-ns rise/fall. As with Digital ADC IP, this solution requires very few off-the-shelf passive components.

Putting it together

Historically, FPGAs did not lend advantages to analog functions, forcing high-reliability design teams to use non-optimal external analog parts. This is no longer the case, as mil/aero engineers now have robust options for integrating analog functions into any digital fabric, including radiation-hardened FPGAs. By using digital implementations of analog functions from Stellamar, engineers can add critical functionality such as thermal monitoring, redundant power supplies and clocking functions–all without adding weight, power or size to the design. The digital synthesis and test methodology ensures the operability and greatly increases reliability.

Further, designers can easily leverage these technologies across projects and across the whole organization. With budgets being slashed and performance more important than ever, these digital IP cores give mil/aero engineering teams the flexibility and productivity they need to meet critical mission objectives.

About the authors

Allan Chin is CEO of Stellamar

Luciano Zoso
is CTO of Stellamar

For more information about Stellamar cores, call (480) 664-9594 or go to

This article was originally published in the first quarter issue of the Xcell Journal,

See related links

. Xilinx rad-hard FPGA reaches for the stars
. Optimizing FPGAs for power: A full-frontal attack
. Image sensor color calibration using Zynq-7000 SoC
. FPGA-based instrumentation withstands chill in deep space
. Embedded vision: FPGAs’ next technology opportunity
. Xilinx FPGAs beam up next-gen radio astronomy

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