Improving fault coverage for random-pattern-resistant designs
Designs with LogicBIST exhibit random pattern resistance because of the random nature of LBIST vectors, thus leading to low fault coverage. To handle this, we insert test points with the help of random resistant fault analysis (RRFA). The computation of the fault detection capability of a design with LBIST is done with the help of fault simulation, which gives an estimate of “quality of test”. We discuss these in more detail below, along with techniques to increase fault detection in LBIST designs.
Fault targeting with LogicBIST
Test through LBIST is a pseudo random test unlike the production scan test which is more deterministic test. The scan vectors in LBIST are generated by a Pseudo Random Pattern Generator (PRPG) which generates pseudo random sequences. Whereas in the case of production scan testing the scan vectors are deterministically fed through the scan inputs through the Automatic Test Equipment (ATE).
Due to the random nature of LBIST test it is not always possible to test particular faults because of no direct control on what sequence of scan inputs is being shifted in the design. Problems arise when LBIST is implemented on designs which are combinational intense or have large combinational paths between the registers. These designs may become resistant to random patterns which means the probability of controlling some nodes randomly to a 0 or 1 value, or the probability of observing some nodes to a scan-register is low, assuming random and equally probable inputs being fed to the design.
Taking example of an AND gate in Figure 1 we calculate the probability of controlling the output of the gate to a value ‘1’. The diagram below shows the probability of each node getting a value of ‘1’ or ‘0’. Format P(1) / P(0).
Figure 1: Controllability for 2 input and gate
Figure 2 the probability of getting ‘0’ or ‘1’ value at the different nodes when the combinational depth is increased by one. The probability of getting ‘1’ at the output of this combinational block is 1/8. However this is still a very simple combinational block, and we see complex blocks in real design. So, as the combinational depth increases the ability to control the nodes to a particular value decreases.
Figure 2: Controllability for 2 depth combo logic
Such designs show resistance to random pattern when tested with LBIST and may lead to low fault coverage. To handle such scenarios we often insert points to improve the design’s testability. Test points can be categorized in two types: Control points and observe points.
Controls Points increase the probability of a particular node getting controlled to a ‘0’ or ‘1’ value. Both type of control points are shown in Figure 3 and Figure 4, where AND type of control point increases the probability of node getting controlled to a ‘0’ value whereas OR type of control point increases the probability of node getting controlled to a ‘1’ value.
Figure 3: AND type control point increases the controllability to value ‘0’
Figure 4: OR type control point increases the controllability to value ‘1’
Observe points make the hard to observe nodes of the design easy to observe to some scan-flop. When multiple nodes of the design are to be observed those nodes are tapped XORed and fed to the scan flops. One example implementation of observe point is shown on Figure 5.
Figure 5: Observe point
The identification of test points is done using random resistant fault analysis (RRFA) method. The identification works by collecting statistical data during fault simulation for a small number of random test patterns. Controllability and observability measures of each signal in the circuit are calculated and is given a weight by measures of delta coverage gains using probability models. Based on the analysis of the data from fault simulation RRFA lists the possible candidates for the test point insertion and categorizes them as control0/1 or observe point.
LogicBIST fault simulation
Fault simulation is an important tool/method to analyze the circuit from the view of fault detection. The fault simulation process emulates the node faults in a design in order to determine which faults are detected by a given set of test vectors. As discussed in the previous section RRFA uses fault simulation to identify the suitable candidates for test point insertion by analyzing the probability of node controllability and observability in the presence of random stimulus or test vector.
Similarly when the design is LBIST inserted, we fault simulate the shift and capture procedures on the design and determine which faults are covered by the LBIST vectors. The output of this process is the fault coverage report and final LBIST signature (MISR) which is used as an expected response of the design. The fault simulation process can be modified in terms of inputs to get a different fault coverage and the signature.
Figure 6 shows the fault simulation flow specifying the inputs to the system and the outputs from it. The effects of changing the inputs and how the outputs are used are discussed ahead.
Figure 6: Fault simulation flow: Inputs and outputs
Starting with the inputs to the fault simulation system, we will discuss how these inputs have effect on the output of the system.
Firstly, the design should be LBIST compliant, meaning it should be scan stitched and should have all X sources masked in the design. X sources are logic whose state is not deterministic and is unknown to the fault simulation system. Some type of X sources are, non-driven inputs of the LBISTed logic, outputs of analog blocks, tristate buses, timing exceptions etc. These X sources should be blocked by using appropriate x-blocking mechanism.
Second input to the system is the PRPG SEED value. The seed value determines what would be sequences of shift data fed to the design. To find the best seed value for maximum coverage one may have to go through multiple fault simulations or fault simulation engine may itself compute the optimal seed.
Third input to the system is the constraints and shift-capture sequences. The MISR and fault detection also depends on the number of LBIST patterns, shift length of the design, static constraints and sequences in which the capture pulses are applied.
Figure 7: Factors affecting fault coverage
The more the number of number of patterns run during LBIST the more would be the fault detection. Generally the number of patterns depends on the application use case. For example in case of production test we may not have any hard restriction in terms of number of patterns but in case of on-field self-test the device is required to respond within a certain duration of time, so the number of patterns needs to be optimal but achieving maximum coverage in minimum time.
The fault simulation engine requires the design to be set in the constrained environment for the LBIST mode execution. These constraints are fed to the engine as case settings which are static or may vary across patterns. These case settings along with the shift- capture clock sequences help the fault simulation engine to simulate the design cycles and compute the final MISR.
Shift and capture sequences of clocks can be hardwired or programmable feature of the LBIST controller. This determines how the different clock domains are pulsed. This sequence greatly impacts the fault detection therefore it is important to optimize these sequences. It should tried to give maximum number of patterns to largest clock domain. Increasing the sequential depth for capture depth also gives increased coverage and also helps is pattern reduction.
Figure 8: Clock Shift and Capture Sequences
In-field LBIST testing is a must for devices used in critical applications like military and automotive. The testing targets are also very stringent to achieve maximum fault coverage in the minimum possible time. The fault detection capability of the LBIST controller determines the quality and time of testing, and depends on parameters like clock sequencing, intelligent selection of seed for PRPG, and number of control and observed points added, as discussed. To achieve maximum coverage, proper analysis and optimization of the design, and use of the techniques described, should guide your LBIST testing.
A new built-in TPG method for circuits with random pattern resistant faults, Kavousianos, X.; Bakalis, D.; Nikolos, D.; Tragoudas, S.
M. F. Alshaibi and C. R. Kime, “MFBIST: A BIST method for random pattern resistant circuits,” in Proc. Int. Test Conf. , 1996, pp. 176–185
VLSI Test Principles and Architectures: Design for Testability Xiaoqing Wen, Laung-Terng Wang, Cheng-Wen Wu
Method and apparatus for programmable LBIST channel weighting Patent US6671838