# Improving peak current-mode control

A flyback converter is designed to operate over a specified input voltage range, with a given output voltage and maximum output current. The worst-case design normally is done at the minimum input voltage and maximum output power. In the real world the maximum power delivered at high input line may double that of the power delivered at the minimum input line voltage. This forces power-supply designers to over design the power stage. This article discusses the reason for the increased input power increase and methods to reduce it. It also shows a novel method to improve the performance of peak current-mode control.

The flyback converter transformer basically is two coupled inductors. During the time when the primary switch is on, energy is stored in the primary coupled inductor. Because of the transformer’s primary and secondary winding configuration, when the primary switch is on, the output diode (D1) is reverse-biased (**Figure 1a – 1b**). When the primary switch is off, the energy stored in the primary coupled inductor is then transferred to the output coupled inductor, providing power to the load. The flyback transformer can step up or step down the output voltage, and provides input to output isolation.

*Figure 1. 1a) Stored energy in the primary figure; 1b) energy transfer to secondary.*

**Peak current-mode control**

For cost and simplicity the flyback converter typically is used in peak current-mode control, so the output current is not directly measured. When the flyback converter is in an overload fault the output voltage drops. As a result, the feedback compensation voltage rises beyond the pulse-width modulators (PWM) controllers current limit threshold and the PWM operates in pulse-by-pulse current limit. In pulse-by-pulse current limit the feedback voltage no longer controls the PWM duty cycle. The duty cycle is terminated when the peak primary current exceeds the PWM controller current limit comparators voltage reference (V_{CS}).

**Challenges with peak current-mode control**

When the controller is in pulse-by-pulse current limit the primary switch can’t be turned off instantly. There are propagation delays within the PWM and power stage, which include the controller’s leading edge blanking (LEB), and propagation delay in the current limit comparator, logic circuits, gate driver, and turning off the power MOSFET. Propagation delays cause the peak primary current to be higher than expected due to overshoot.

**Equation 1** calculates the actual peak primary current:

(1)

After calculating the peak primary current, we can use **Equation 2** to calculate the input power:

(2)

**Calculate slope**

These propagation delays can be several hundred nano seconds long. Using **Equation 3** we can calculate the slope of the primary current, where V_{IN} is the rectified dc line voltage, L_{P} is the transformer primary inductance, and *dt* is the total propagation delay.

(3)

With a fixed propagation delay (dt in **Equation 3**), as V_{IN} increases the slope of the primary current also increases. Because the of the propagation delay, the peak current at the maximum V_{IN} will be higher than the peak current at the minimum V_{IN} because of the overshoot (**Figure 2**).

**Click on image to enlarge.**

*Figure 2. Propagation delay vs. V*

_{IN}.
The result is that the input and output power increases as the input line voltage increases. An example illustrates the problem. The peak primary current (**Equation 4**) is based on these systems requirements:

(4)

For peak current-mode control, after we calculate the peak current, we can size the current sense resistor (**Equation 5**).

(5)

V_{CS} is the PWM current limit comparator voltage reference (0.5V). The peak current overshoot at the minimum input voltage is:

At the maximum input line the peak current is (**Equation 6**):

(6)

**Forced to over design**

The analysis shows that the input power, which is calculated at the minimum input line voltage, increases from 6.81W to 8.12W, which is a 16.1% increase. This forces power-supply designers to over design the power stage. **Figure 3** is a plot of V_{OUT} versus the output current (I_{OUT}) of a power supply operating with peak current-mode control.

*Figure 3. Peak current-mode control V*

_{OUT}vs. I_{OUT}.
**Novel implementation of peak current-mode control**

To improve the performance of peak current-mode control, a novel method of biasing up the peak primary current as seen across the current sense resistor was developed, line current limit feed-forward. In the flyback converter topology we can take advantage of the transformer auxiliary winding, which is used to provide bias power to the controller. Referring to **Figure 4**, while the main flyback switch is on, Q1, the voltage on the auxiliary winding is negative and proportional to the rectified line voltage (**Equation 7**).

(7)

Where: naux is the number of turns on the flyback primary (Np) divided by the number of turns on the transformer auxiliary (naux) winding.

*Figure 4. Flyback converter with feed forward.*

The input to the PWM QR pin of the controller is a current mirror. As the voltage on the auxiliary winding goes negative, a current (IQR) proportional to the input rectified line voltage is mirrored by a gain of 100 (**Equation 8**), and injected on to the current sense resistor to offset the current sense voltage (VCS_{OFFSET}). The current into the QR pin is set with a resistor RFF.

(8)

The first step is to force the peak current at the maximum V_{IN} to produce the same input power as we calculated at the low-line input (**Equation 9**). We do that by subtracting the current overshoot as a result of the propagation delay from the input power at the minimum input line.

(9)

Therefore, the required current limit feed-forward as seen across the current sense resistor is (**Equation 10**):

(10)

To inject a 0.0634V offset voltage onto the current sense resistor, we need to calculate the voltage on the transformers Auxiliary winding (**Equation 7**), selecting IQR in a range of 1 mA to 4 mA. For this example, we used 2 mA. Now we can calculate the required RFF (**Equation 10**).

(11)

The current injected on the current sense resistor (Rsense) is the IQR current divided by the current mirror gain of 100 (**Equation 12**):

(12)

The I_{CS} current is injected onto an external resistor (**Equation 13**) that is series with the CS controller pin and the current sense resistor (R_{SENSE}). The result is that the current sense resistor has a biased that is proportional to the input line voltage. This turns-off the peak current earlier, forcing the input power at the minimum input line to be approximately equal to the input power at the maximum input line.

(13)

**No over design**

Peak current-mode control in conjunction with line current limit feed-forward eliminates the requirement for power supply designer to over design the power stages. This reduces the cost, as well as being a low-complexity solution for power supplies and battery chargers.

**References:**

1. Abraham Pressman, Keith Billings, Taylor Morey, *Switching Power Supply Design, Third Edition*, the McGraw-Hill Companies, April 17, 2009.

2. Christoph Basso, **"The Over Power Phenomenon,"** How2Power TODAY, October 2010.

For more information visit: **www.ti.com/power-ca**.

**Terry Allinder **is a principle applications engineer for Texas Instruments Power Products Division. He has over 30 years of power electronics experience as an Application Engineer and power supply designer for military applications. He received his BSEE from California Polytechnic University, Pomona. Terry can be reached at ti_terryallinder@list.ti.com.