An in-chip sensor fabric developed by Moortec (Plymouth, UK) can be used on TSMC’s N6 process for a broad array of chip designs currently being developed from high-to-mid end mobile, consumer applications, AI, networking, 5G infrastructure, GPU, and high-performance computing.
The sensor fabric monitors key chip parameters both during production test and the measurement of realtime dynamic conditions. The in-chip sensing is an essential element to achieving the highest levels of performance and reliability within today’s advanced process technologies, underpinning optimization schemes, telemetry and semiconductor lifecycle analytics. The thermal sensor has already been developed for the 5nm N5 process (see below).
“We are hugely excited to be providing our complete sensing fabric solution to the design ecosystem for TSMC’s N6 process, which demonstrates that despite recent global events, Moortec is still ‘open for business’ and able to deliver compelling product,” said Stephen Crosher, CEO of Moortec.
“Our long-term collaboration with TSMC has allowed us to listen closely to customers and understand their needs, which in turn allows us to deliver the sensing solutions that provide real-time insights deep within the chip, ensuring optimal device performance and reliability for early-to-market customers.”
The N6 process is a variant of the 7nm N7 process with the same design rules but an 18 percent reduction in size, allowing the 7nm designs to be reused.
“TSMC N6 technology will further extend our leadership in delivering product benefits with higher performance and cost advantage beyond the current N7,” said Dr. Kevin Zhang, TSMC Vice President of Business Development. “Building upon the broad success of our 7nm technology, we’re confident that our customers will be able to quickly extract even higher product value from the new offering by leveraging a well-established design ecosystem today.”
Next: TSMC 6nm
“We’re pleased with the result of our collaboration with Moortec in delivering its sensing solution on TSMC’s N6 process to address the design challenges on increased computing power for leading-edge mobile and high performance computing applications,” said Suk Lee, Senior Director of Design Infrastructure Management Division at TSMC.
“We look forward to a continued partnership with Moortec to support our mutual customers with design solutions benefiting from the power and performance boost of TSMC’s most advanced process technologies and quickly launch their new product innovations to market.”
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