India prepares RISC-V processors
If funding is released as expected, the Centre for Development of Advanced Computing (C-DAC), a branch of India’s Ministry of Communications & Information Technology, could tape out a 64-bit RISC-V processor in about 30 months, said Biju C. Oommen, a senior manager in C-DAC’s chip design unit. The team consists of about 70 engineers who have designed a wide variety of 8- to 32-bit processors and SoC blocks.
The team has worked on chips for both government and commercial users ranging from an energy metering IC to a digital programmable hearing aid and an automotive controller. C-DAC was created in 1988 to develop supercomputers after the U.S. banned export of the systems to India and expanded to cover a wide variety of high tech projects.
The VLSI team plans to design a quad-core processor running at up to 2 GHz. “This is more complex than any other processor we have designed, we have not taped out anything beyond a 32-bit processor to date,” said Oommen.
The design could deliver variants for a wide range of public and private customers. Targets could include tablets or gateways for the Internet of Things.
Separately a team of about 30 designers at IIT Madras has been working for more than two years on a family of 32- and 64-bit open source processors based on RISC-V. The work started about five years ago under the name Shakti which means power because the chips originally used IBM Power cores.
The Shakti project now includes plans for at least six microprocessor designs as well as associated fabrics and an accelerator chip. A significant amount of code for at least two of the RISC-V parts is now available, a high-end out-of order design and a simpler three-stage processor geared for IoT.
“We focus on IoT devices partly because that’s a buzzword, there’s a requirement in India for them and most volumes are there, be we also have a five-stage pipeline design for higher end embedded stuff,” said G. S. Madhusudan, a principal scientist working on the project at IIT Madras.
The team hopes to have Linux up and running on one of the cores in an FPGA implementation this summer. The design is still in an early phase such that “you wouldn’t want to tape it out,” he said.
The project also has a mandate from its funders to help develop an alternative ecosystem for servers in India, driving its high-end designs.
“It’s not necessarily to replace Intel…I am a server guy…and where else would you get to work on a processor to compete with Xeon,” he said.
The team includes three senior engineers new to academia with much of the work done by students and post docs. The budget is fairly modest, with typically less than $20,000 a year spent on salaries.
That said, Madhusudan said he expects at least one startup will be formed soon to develop a variant of a Shakti chip targeting government requirements for high security. A so-called tagged instruction set would create a chip with the memory address of each location tracked in a design similar to one in the works by Draper Labs for the U.S. government.
The development of a new server “will take some more time but there are significant needs in the India defense department where they have ambitious plans including three aircraft carriers in budget,” he said.
An accelerator in the works for big data analytics could become more important than another server processor. Researchers in Madras and Purdue University have scoped out a concept for a neuromorphic accelerator that does not use the RISC-V ISA but would use a custom open source core and use one of the RISC-V processors as its host.
Among other microprocessor efforts in India, funding of about $50 million for research on neuromorphic cores is said to be coming together for academics in Bangalore. In another effort, researchers at IIT Bombay are said to be at work on a smaller Sparc V8-based processor design.
About the author:
Rick Merritt, Silicon Valley Bureau Chief, EE Times