Industry’s first 4-state emulation and mixed-signal modeling to accelerate SoC verification

Industry’s first 4-state emulation and mixed-signal modeling to accelerate SoC verification

Technology News |
By Nick Flaherty

Cadence Design Systems has developed a portfolio of applications that significantly enhance the capabilities of its flagship Palladium Z2 Enterprise Emulation System.

The domain-specific apps allow customers to manage increasing system design complexity, improving system-level accuracy and accelerating low-power verification for advanced applications, such as artificial intelligence and machine learning (AI/ML), hyperscale and mobile. The apps have already been used by Nvidia, Mediatek and Samsung.

The apps include the industry’s first 4-state emulation capability enables acceleration of simulations requiring X-propagation such as for low-power verification of complex SoCs with multiple switched power domains.

The Real Number Modeling App provides the industry’s first real number model emulation capability enables acceleration of simulations on mixed-signal designs.​

A next-generation massively parallel architecture for multi-billion-gate, million-clock-cycle power analysis of complex SoCs is up to 5X faster than its previous versions and provides dynamic power analysis.

“Nvidia has utilized Cadence Palladium Emulation for many years for our early software development, hardware-software verification and debug tasks,” said Narendra Konda, vice president, hardware engineering at Nvidia.

“We have worked closely with Cadence to provide input on the new Palladium apps, including the industry’s first Real Number Modeling and 4-State Emulation apps. Using the new apps, we can accelerate and integrate real number modeling constructs as part of our large GPUs, improving system-level accuracy of analog, digital and software behaviours and accelerating our time to market.”​

“MediaTek’s innovative SoCs across mobile, smart home and IoT applications continue to grow in complexity to meet increasing customer performance demands. With Cadence’s next-generation Dynamic Power Analysis App for the Palladium Emulation System, we are seeing a 5X acceleration for power analysis and direct report generation for our advanced SoC designs compared to the previous version,” said Debra Lin, deputy director, MediaTek

“Samsung requires best-in-class emulation to develop our most advanced and complex SoCs, and we have utilized the Cadence Palladium Emulation System for many years. With the new 4-State Emulation App, we can accelerate the low-power verification of our complex SoC designs, improving our verification accuracy and low-power coverage while improving overall verification throughput,” said Seonil Brian Choi, vice president at Samsung Electronics.

“To keep up with today’s advanced SoC design requirements, customers need an emulation solution that offers high performance with fast, predictable compile and debug,” said Dhiraj Goswami, corporate vice president, Hardware System Verification R&D at Cadence. “With the release of these new Palladium Apps, for the first time in our industry, our customers can now accelerate X-propagation and mixed-signal on emulation.”

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