Industry’s first open source ASICs from crowd-sourced collaboration
In the partnership, in which the MPW shuttle was managed by Efabless and manufactured at SkyWater using the company’s publicly available 130-nm open process design kit, open source designs were selected to be fabricated at no cost to designers. The design submission process was open for 30 days, generating 1700 downloads in the first two weeks and filling all 40 available slots.
“With design tools and open source design IP, engineers from around the world are collaborating and creating new content while accessing design and fabrication resources in a revolutionary way,” says John Kent, SkyWater executive vice president of technology development and design enablement. “Engineers are refining and adding content to the body of knowledge on a continuous basis. This is both an industry first and a significant step forward in design enablement.”
The program, say the companies, illustrates the potential of applying open source to all levels of IC design to improve access to resources such as design tools, IP, and foundry process design kits (PDKs) that can be shared by a larger pool of individuals with specialized skill sets. To enable wider engagement from the community, Efabless has developed Caravel, a carrier RISC-V based System on Chip that includes all the housekeeping functions that support users’ designs and acts as a standard test harness.
This is designed to further reduce barriers to design, prototyping and verification. Every project owner will receive four development boards with their design plus additional parts for other uses.
The Open MPW Shuttle Program attracted designers from both academia and commercial organizations. Approximately 60% of the designs were submitted by software, FPGA, and hardware developers (non-IC experts) — demonstrating a significant untapped underlying interest generated by putting IC design in the hands of users, say the companies. By enabling open source design, the program also illustrates the diversity and creativity of designs that could be generated.
Examples of submitted designs include:
- OpenPOWER SoC
- 5 RISC-V SoCs
- Crypto-currency Miner
- Robotic App Processor
- Amateur Satellite Radio Transceiver
- Analog/RF
- Four eFPGAs
“We have seen fantastic community engagement with almost 1100 members,” says Mohamed Kassem, Efabless chief technology officer and co-founder. “On this first MPW, this project empowered and enabled dozens of new designers to bring their ideas to silicon. This was achieved by focusing on their new designs which were later integrated in our standard harness SoC, Caravel. We just taped-out the first shuttle and we are looking forward to silicon validation.”
Generated IP will be accessible by all open source designers going forward on the 130 nm mixed-signal process (SKY130) at SkyWater. Designers will be able to utilize the Efabless platform to prototype these designs, derivatives of these designs, and new designs that combine the open source designs with proprietary IP from traditional providers.
The SKY130 process, a mixed-signal CMOS technology, offers many normally optional features as standard – features like the local interconnect, SONOS non-volatile memory functionality, MiM capacitors and more, providing designers with a wide range of flexibility in design choices. Professors from several universities including Stanford, UC Berkeley, Purdue University, and the American University in Cairo have used the SKY130 process as a base technology for academic projects.
Additional designs, say the companies, will be accommodated starting in the next MPW shuttle run, which is anticipated in mid-2021. The open source foundry PDK is accessible at https://github.com/google/skywater-pdk.
More details about the design submission process and requirements can be found by visiting:
- https://efabless.com/open_mpw_shuttle_project_mpw_one
- https://www.skywatertechnology.com/mpw/open-source-mpw-program/
Related articles:
Google sponsors open source manufacturing of custom ASICs
Efabless launches open-source hardware design portal
Advanced semi design services tie-up targets emerging applications
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