Industry’s first reference clock multiplier for receiver test
This solution supports multiple reference clock rates ranging from 19 to 100 MHz for receiver test applications such as PCIe® 1.x, 2.x and 3.0 main boards, MIPI M-PHY devices and UHS-II host devices. The use of the reference clock multiplier significantly simplifies the receiver test setup, helping R&D and test teams to accurately characterize and verify standard compliance under easy to reproduce test conditions.
With common reference clock architectures, where the host cannot run on an external reference clock, it is necessary to lock the generated stressed-pattern signal to the reference clock from the receiver under test. That’s because the receiver under test also derives its sampling clock from this reference clock. Not locking the stressed pattern generator to the same reference clock would lead to wrong and non-reproducible jitter-tolerance test results.
Some emerging and existing standards require this test topology: the PCI Express® rev 2.x and 3.0 CEM specifications from the PCI-SIG®, the MIPI M-PHY draft specification from the MIPI alliance, and the draft SD card specification for UHS-II host devices use a common reference clock architecture. In the past it was very cumbersome to reproduce such setups and it was not easy to reproduce stress conditions, especially when spread-spectrum clocking and low-frequency jitter components are present on the reference clock signal.
The N4880A reference clock multiplier provides a multiplying phase locked loop (PLL), which enables users to lock the pattern generators of the J-BERT N4903B high-performance serial BERT and the ParBERT 81250A to such a reference clock. SSC and jitter are fed through the N4880A up to the PLL bandwidth.
At its reference clock input, the N4880A supports multiple clock rates: 100 MHz for PCIe 1.x, 2.x and 3.0 CEM test; 19.2 to 52 MHz for MIPI M-PHY gear 1, 2 and 3 devices; and 26 to 52 MHz for UHS-II host devices. The bandwidth of the multiplying PLL automatically adapts. Users can control the settings of the N4880A from a stand-alone user interface running on a Windows PC via a USB connection.
A key benefit of the N4880A reference clock multiplier is precise and reproducible receiver tolerance testing by emulating real-world clock conditions. This is achieved by transparency to low-frequency jitter and SSC profiles from the system under test, its tolerance of huge amounts of SSC for UHS-II reference clocks and its low input sensitivity to handle very low voltage levels.
The N4880A reference clock multiplier also delivers higher R&D efficiency enabled by reduced complexity of test setup and ensures investment protection by supporting multiple reference clock rates ranging from 19 to 100 MHz and support for J-BERT and ParBERT external clock mode, for PCIe 1.x, 2.x, and 3.0, SD card UHS-II, and MIPI M-PHY.
For further information: www.agilent.com/find/n4880.
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
