Infineon halves power wafer thickness
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Infineon has cut the thickness of its silicon power wafer in half to 20µm, reducing the on resistance by 40% and the overall power losses by 15%.
“This is a technology breakthrough from Infineon, the thinnest power wafer at a staggering 20 microns,” said Adam White, resident of the power and sensor system division at Infineon. “This reduces the wafer substrate resistance by 50% and reduces the power losses by 15%. By reducing the thickness of the wafer you get better power losses in the system.
The process, developed at Villach in Austria, will be used for 12V devices for the local power conversion for next generation AI GPUs, TPUs and CPUs with vertical power. These require high currents of 1000 to 2000A at voltages of 0.8V from a 5V, 12V or 48V power rail and there are multiple topologies to provide this, says White.
“For 10 to 12V transistors this allows 40% lower RDSon, that is unparalleled so we think there will be a lot of interest from the industry at 40V and below. We have already engaged with AI customers.” Other applications include consumer, motor control and computing.
“There is also a 3 [percentage point] efficiency gain at 50A with chip design optimization, new driver designs and next generation MOSFETs that will be built on this ultrathin technology,” he said. The thinner wafers also enable backside power connections with less effort.
White is reluctant to talk about the handling required for the thinner wafers. “The systems and handling of the 300mm wafers are the main hurdles you have to overcome,” he said. “It really does involve specialised handling but there are special steps that we have to follow.
The process is similar to that for the 40um wafers launched in 2016 but with additional process steps. “That shows how long it took to develop,” said White. “There is no additional complexity, we are not bringing in a process that needs additional capex, we are adding a couple of steps to get down to 20 microns. When you are processing wafers on silicon substrates the processing is quite remarkable,” he tells eeNews Europe.
The silicon wafer process will run alongside silicon carbide and gallium nitride.
“We need to be mastering all three technologies and silicon will continue to dominate in a number of areas,” he said. “Our ramp at Kulim on 200mm SiC wafers is going to plan, and we also announced the world’s first 300mm GaN power wafer with benefits at high frequencies, anything above 5MHz.”