Infineon rolls multicore automotive microcontroller architecture

Infineon rolls multicore automotive microcontroller architecture

New Products |
By eeNews Europe

Infineon’s multicore architecture features up to three processor cores to share application load, introduces lockstep cores and contains further enhanced hardware safety mechanisms. A first implementation of the architecture is available to selected customers for architecture exploration and early prototyping.

Based on Infineon’s existing TriCore processor architecture, the new multicore architecture sets another benchmark for real-time performance in automotive applications, the company claims. It contains up to three TriCore processor cores connected over a crossbar running at full CPU speed and avoiding hardware contentions. Additionally, the architecture implements multiple program Flash modules with independent read interfaces which further support the real-time capability.

Additional innovations of the architecture comprise a new easily applicable and powerful timer module which offloads the CPUs, and new Analog to Digital Converters including Delta Sigma converters with high accuracy and high sampling rate.

The 65nm embedded Flash silicon process technology and the microcontroller architecture are designed to balance increased performance with the need for lower power consumption. Additional low power modes are supported to enable very low standby current consumption.

Infineon’s multicore architecture introduces leading edge methods to efficiently meet the newly introduced ISO 26262 Automotive safety standard. Design, implementation and documentation are focused for compliance to the highest Automotive Safety Integrity Level (ASIL D). This ensures that safety system development efforts are reduced to a minimum.

Two of the three TriCore CPUs feature additional Lockstep cores which can be configured independent of each other. Further implemented safety techniques include, for example, safe internal communication buses, a bus monitoring unit and both error detection code (EDC) and error correction code (ECC) on all memories. A distributed memory protection system operates on core level, bus level and on peripheral level. These enhanced encapsulation techniques allow the integration of software with mixed criticality levels from different sources, allowing seamless hosting of multiple applications and operating systems on a unified platform.

The multicore architecture features a hardware security module (HSM) to meet upcoming security requirements to better protect automotive applications from tampering or potential hacking attacks. The HSM uses leading edge hardware-based security technology.

The 65nm embedded Flash technology is designed for highest reliability in the harsh automotive environment. End-of-line programming speed of the embedded Flash is up to 20 times faster than in the previous generation of Infineon’s microcontrollers. This is particularly relevant due to the increased amount of embedded Flash required by future automotive systems.

The new multicore architecture will initially be implemented in the next generation 65nm AURIX eFlash microcontroller family. This product family will be highly scalable with devices of up to 300MHz in clock frequency and up to 8MB of embedded Flash. With its high real-time performance, embedded safety and security features the microcontroller family is ideally suited for applications such as the control of combustion engines, electrical and hybrid vehicles, transmission control units, chassis domains, braking systems, electrical power steering systems, airbags and advanced driver assistance systems.

First products of the AURIX family are scheduled to be available by mid 2012, with qualification planned in the second half of 2013.

Further information on Infineon’s automotive semiconductor portfolio and on the automotive microcontrollers are available at and


If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles