Integrated multiplexed input ADC saves PCB area, power, and cost for high channel count systems

Integrated multiplexed input ADC saves PCB area, power, and cost for high channel count systems

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By eeNews Europe

Multi-channel precision data acquisition systems used in industrial, instrumentation, optical communication and healthcare applications are driving the demand for high channel count, low power and compact form factors to address the increased printed circuit board (PCB) density and thermal power consumption challenges. System designers make trade-offs in performance, thermal stability, and PCB density to maintain optimum balance and they are continually pressed to find innovative ways to tackle these challenges while minimising overall bill of material (BOM) cost.

The proposed low power solution using an integrated multiplexed input 8-channel, 16-bit, 250 ksample/sec PulSAR ADC AD7689 available in a miniature, wafer level chip scale package (WLCSP) footprint saves over 60% board space for these applications while offering precision performance and flexible configuration.

Multichannel data acquisition systems typically employ either discrete or integrated multiplexed and simultaneously sampled analogue signal chains for interfacing with various sensor types such as temperature, pressure, optical, vibration, and many more based on the application requirements. Some applications require simultaneous sampling to obtain increased sampling rate per channel and to preserve the phase information among different channels. The key benefit of multiplexing is fewer number of ADCs per channel required, resulting in reduced space, power and cost. However, the achievable throughput rate in a multiplexed system is the single ADC throughput rate divided by the number of channels being sampled.

The Successive Approximation Register (SAR) analogue-to-digital Converters (ADCs) offer inherent merits of low latency and dynamic power scaling with throughput. They are often used in channel multiplexed architectures ideally suited for sensing and monitoring functions. Multiplexed data acquisition systems used in optical transceiver modules need high channel density and wearable medical devices require small form factors and low power, where the signals from multiple sensors need to be monitored and multiplex many input channels in to a single or several ADCs.

One of the main challenges with multiplexed data acquisition systems is that when the input is switched to next the channel, it requires fast response to step input near full scale amplitude without any settling time or crosstalk issue. The following section presents a real world use case of SAR architecture based multiplexed input ADC for optical transceivers and indicates why the ADC is ideally suited for this type of application.


Optical transceivers

The market for 100 Gbps optical transceivers is uniquely positioned to grow in the next decade, for high-speed coherent optical transmission. The key challenge for optical transceivers is to acquire and process wider bandwidth signals or multiplex number of input channels at lower power in a smaller footprint. The size, power, and cost structure of today’s transceivers, originally designed for long-haul applications, limit their utilisation in more cost-sensitive metro networks. The metro networks include: metro regional 500 km – 1000 km, metro core 100 km – 500 km and metro access, under 100 km, applications. Due to fierce competition in metro networks, the space comes at a high premium, making line-card density extremely crucial and consequently, a path to a lower-cost optical line cards or pluggable modules in a smaller footprint has become increasingly important for coherent applications.

In optical networks, as bit rates per channel increases from 10 Gbps towards 100 Gbps and higher, the optical fibre non-idealities severely degrade signal quality and affect its transmission performance. Technical challenges arise also in long-haul optical networks when the penalties occur in terms of optical noise, non-linear effects, and dispersion due to optical fibre impairment.

To address these significant challenges, various manufacturers of 40G and 100 Gbps optical transceivers use coherent technology that allow higher data rate connectivity with maximum reach at longer distances for metro long haul, long-haul and ultra-long-haul networks. The coherent technology generally combines multi-level signal formats and coherent detection using dual polarisation, quadrature, phase-shift keying (DP-QPSK) for optimised signal modulation, allowing immunity to fibre impairments at higher data rates and making 100 Gbps transmission economically and technically feasible.

The next generation of 100 Gbps (and above) data rate optical transceivers will require lower power consumption and miniature form factor to allow increased channel density for significant space, power and cost savings. Depending on requirements, the channel count typically varies anywhere from eight to 64 in an optical system. The component placement and trace routing become dominant for the PCB designers, especially for high channel density system.

A simplified block diagram of generic optical module is shown in Figure 1, which includes transmitter, receiver, micro-ITLA (integrated tunable laser assembly) and data acquisition components. Figure 2 shows the simplified block diagram of micro-ITLA, which is a wideband electronically tunable laser device and controls rapid wavelength switching. The transmitter includes Mach-Zehnder driver and modulator to control the amplitude or intensity of the exiting laser light. The multiplexed input ADC is typically used in control and monitoring functions to digitise the data from the multiple channels in optical module and micro-ITLA.

Figure 1: Simplified block diagram of optical module

Figure 2: Simplified block diagram of micro integrated tunable laser assembly


Integrated multiplexed-input, 8-ch, 16-bit, 250 kSPS ADC

The ADC is an integrated multiplexed input 8-channel, 16-bit, 250 ksample/sec SAR based ADC manufactured on Analog Devices’ 0.5 μm CMOS process. The integrated 8-channel low crosstalk multiplexer introduces minimal mismatch from between adjacent channels and allows sequential sampling.

The ADC allows the choice of a very low temperature drift internal 2.5V or 4.096V precision voltage reference, an external reference, or an external buffered reference and on-board temperature sensor allows monitoring typical internal temperature of the ADC. This eliminates the need for external components, significantly saving PCB area and BOM cost. It includes a channel sequencer useful for scanning channels as singles or pairs, with its internal temperature sensor enabled or disabled in a repeated fashion. It offers a flexible serial digital interface compatible with SPI, MICROWIRE, QSPI, and other digital hosts.

Its 14-bit internal configuration register allows the user to select various options including a number of channels to be sampled, reference, temperature sensor and channel sequencer. The interface allows 4-wire read during conversion, read after conversion and read spanning conversion modes with and without busy indication. The ADC is ideally suited for high channel density applications such as optical transceivers, wearable medical devices and other portable instruments for a precision sensing and monitoring.

Figure 3 shows a simplified ADC block diagram for a multi-channel data acquisition system, which offers flexible configuration options and precision performance. It solves the complex design issues related to the channel switching, sequencing and settling time and saves design time.

Figure 3: AD7689 simplified application diagram (All connections and decoupling not shown)

For multi-channel, multiplexed applications, some designers use a low-output-impedance buffer to handle the kickback from the multiplexer inputs depending on throughput rate used. The input bandwidths of the SAR ADC (tens of MHz) and ADC driver (tens to hundreds of MHz) are higher than the sampling frequency, whereas the desired input signal bandwidth is typically in the tens of Hz to hundreds of kHz range. Therefore, depending on the system requirements, a single-pole, low-pass RC anti-aliasing filter may be required at the input of the multiplexer to eliminate unwanted signals (aliases) from folding back into the bandwidth of interest, to limit the noise and to reduce settling time issues.

The value of the RC filter used at each input channel should be carefully selected based on the following trade-off because too much band limiting can affect settling time and increase distortion: if the capacitance is large, it will help attenuate the kickback from the multiplexer, but it can also make the previous amplifier stage unstable by degrading its phase margin. C0G or NP0 type capacitors are recommended for an RC filter that has high Q, low temperature coefficient, and stable electrical characteristics under varying voltages. A reasonable value of series resistance should be chosen to keep the amplifier stable and limit its output current. The resistance cannot be too large, or the ADC driver will not be able to recharge the capacitor after the multiplexer kickback.


Compact form factor

The ADC is available in 2.39 x 2.39 mm pin-compatible wafer level chip scale package (WLCSP), which is over 60% smaller form factor compared to its existing 4 x 4 mm lead frame chip scale package (LFCSP) or other competitive device of its class, allowing increased circuit density in a small system footprint. Figure 4 compares the WLSCP with a size of standard 6 mm pencil.

Figure 4: Size Comparison of the ADC Wafer Level Chip Scale Package with standard pencil

Precision performance

For applications that require multiple ADC devices, it is more effective to use the internal reference buffer to buffer the external reference voltage, thus reducing SAR conversion crosstalk. The best SNR is achieved with a 5V external reference since the internal reference is limited to 4.096 V. It offers an excellent AC and DC performance in terms of INL of ±1.5 LSB, Signal to Noise plus Distortion ratio (SINAD) of ~93 dB and effective number of bits (ENOB) of ~15.2 bits using a 5V external reference for a 2 kHz input tone while running at the full speed of 250 kSPS. Figure 5 shows the typical performance of SNR, SINAD and ENOB for a given external reference voltage utilised.

Figure 5: AD7682/7689 SNR, SINAD and ENOB versus Reference Voltage


Power consumption

The ADC requires an analogue and digital core supply (VDD) and a digital input/output interface supply (VIO) for a direct interface with any logic between 1.8V and VDD. The VDD and VIO pins can also be tied together to save on the number of supplies required in the system, and they are independent of power supply sequencing. Powered from +5V (VDD) and +1.8V (VIO) supplies, its power scales linearly with throughput rate, enabling very low power consumption typically around 1.7 µW typ at 100 SPS and 12.5 mW at 250 kSPS with a 5V external reference as shown in Figure 6. This makes the ADC power efficient and well suited for both high and low sampling rates even as low as a few Hz and for portable and battery powered systems. One of the key features of this part is that it powers down automatically at the end of each conversion phase and consumes a very low standby current of typically only 50 nA, allowing conservation of battery when the device is not utilized and hence extending battery life.

Figure 6: AD7689 Operating current vs throughput

PCB layout and assembly guidelines

The PCB layout for high channel density data acquisition system board must be designed carefully so that the analog and digital sections are separated and confined to certain areas of the board. The fast switching signals and digital lines, such as CNV or clocks, must not run near analogue signal paths and under the AD7689 to avoid noise coupling in to the system. The crossover of digital and analogue signals should also be avoided. At least one ground plane should be used, which can be common or split between the digital and analogue sections.

In the latter case, join the planes underneath the ADC. The exposed paddle of the device must be soldered directly to the system ground plane for increased reliability of solder joints. The ADC voltage reference input, REF pin and its power supply pins must be decoupled with recommended external 10 μF ceramic capacitors placed as close as possible to the pin and ground. They should be connected using short, wide traces with minimal parasitic inductances to provide low impedance paths for high-frequency currents and reduce the effect of glitches or EMI in the system.

The active side of the of ADC WLCSP die is inverted and can be connected to the PCB using solder balls and its dimensions after PCB assembly are as shown in Figure 7. The actual separation between the surface of the die and the substrate (stand-off) after PCB assembly varies with the amount of solder screen printed on to the substrate and pad diameter.

Figure 7: AD7689 WLCSP dimensions after PCB assembly


The next generation of pluggable optical transceiver modules and other portable systems demand power efficient data acquisition system in a small, low cost form factor. The ADC, with industry leading integration and precision performance, supports a wide range sensors interface and enable designers to differentiate their systems while meeting stringent user requirements. It addresses the increased circuit density and thermal power dissipation challenges for space constrained applications by saving over 60% space compared to its existing LFCSP and offering power efficient integrated ADC solution well suited for both high and low sampling rates applications.

About the author

Maithil Pachchigar is an applications engineer in Analog Devices’ Precision Converters business unit in Wilmington, Massachusetts. He joined ADI in 2010 and supports the precision ADC product portfolio and customers in the industrial, instrumentation, medical, and energy segments. Having worked in the semiconductor industry since 2005, Maithil has published numerous technical articles. He received an MSEE degree from San Jose State University in 2006 and an MBA degree from Silicon Valley University in 2010.

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