Intel carves tiny SRAMs at 14nm
In a preview of at least five papers at the International Solid-State Circuits Conference, one Intel executive also continued to express optimism about the company’s work on 10 and 7nm nodes.
Intel will describe a 0.0500µm2 SRAM bitcell capable of storing 14.5 Mbits per mm2. At 0.6V, the 14nm cell still runs at rates up to 1.5 GHz.
The cell is part of a memory array will be widely used in Intel’s future SoCs such as cellular modems that use hundreds of Mbits on a die, said Kevin Zhang, an Intel fellow.
In another paper, Intel will describe a 14nm serdes transmitter that can signal rates up to 40 Gbits/s using either NRZ or PAM-4 modulation. AT 0.03 mm2, Intel claims it is the world’s smallest transmitter delivering more than 25 Gbits/s.
Another paper will report on a 10 Gbit/s serial link for PCI Express made in the 14nm process. It consumes just 59 milliwatts and takes up 0.065mm2 of silicon area.
Wafers are more complex and expensive in the 14nm process which requires double patterning and thus more masks. However, greater gains in density means overall cost per transistor continued to decline at 14nm, something Intel expects to continue for the next two nodes, said Mark Bohr, an Intel senior fellow, echoing comments made in September.
“Moore’s Law can continue beyond 10nm with new materials and device structures and by close collaboration of process and product designers,” Bohr said. “I still believe 7nm without extreme ultraviolet lithography can deliver improved cost per transistor, but exactly how I’m not ready to disclose,” he said.
Intel’s view flies in the face of the rest of the industry that is saying the new FinFET processes at 14-16nm come at higher costs.
Intel’s 40G transmitter embraces two modulation schemes to keep eyes open.
Intel claims its 14nm SRAM design is the smallest to date.
Intel admits production yields of its 14nm node were delayed due to the increased complexity of more mask steps due to double patterning. But Bohr expressed confidence that should not happen again at 10nm despite the need for triple patterning and even more masks.
We may have underestimated the learning rate with a technology that adds many more masks as 14nm did with multi-patterning. That slowed us down more than expected, but we are up to high yields now with more than one product in production and more coming this year.
At 10nm [we’re] running 50% faster in steps per day through the fab, increasing the rate of wafer movement. I think that will keep 10nm on track…[We’re] getting very good area scaling and cost per transistor reduction in 10nm. In our development fab we’ve sped up the move of wafers to offset the increased number of mask steps.
Bohr declined to comment on what new materials or circuit structures Intel will use beyond its tall, thin fins at 14nm. However, he noted Intel researchers “have published more than a couple papers on III-V devices as one example of a new material being considered by our research group.”
Chip stacks will also become an increasingly important technique “although they will not offer the full benefits of Moore’s Law,” Bohr said.
Intel discussed in September a low cost approach to chip stacks without using costly through silicon vias (TSVs). However, Bohr declined to say whether or when Intel plans to use the approach or any other 2.5 or 3-D chip stacks.
Full 3-D stacks use TSVs, tiny vertical interconnects drilled and filled between chips. The 2.5-D approach puts two or more chips next to each other and connects them links in the substrate on which they sit.
Going forward heterogeneous integration will be increasingly important, but we may not be able to do it all on one chip, so you will see more 2.5- and 3-D integration with each chip tuned for different functions and processes.
The 2.5- and 3-D [approaches] are for two different markets. The 3-D approach is amenable to low-power systems like cellphones, and 2.5-D is better for high performance applications where there are less issues of power delivery and heat extraction. Thus the two have different time lines, but whether one comes before another is not yet knowable.
About the author:
Rick Merritt, Silicon Valley Bureau Chief, EE Times
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