Even though Intel’s 10-nm node is more than four years away, the company is currently hammering out the design rules for the process-and EUV is late for the party. ”EUV is late for (the) 10-nm design rule definition’’ stage at Intel, said Sam Sivakumar, director of lithography at Intel, during a presentation at LithoVision here on Sunday (Feb. 27). LithoVision was sponsored by Nikon Corp.
Still, Sivakumar said that EUV still stands a good chance of being inserted for the company’s 10-nm node-if production-worthy tools are shipped by the second half of 2012. Even then, EUV will be at the ”late end of the spectrum,’’ he told EE Times.
Intel is looking at two vendors for EUV tools: ASML Holding NV and Nikon. ASML is reportedly about to ship a ”pre-production” EUV lithography tool to Intel. That tool from ASML is called the NXE:3100, which is using a light source from Cymer Inc.
For its part, Nikon has devised EUV alpha tools within its own headquarters in Japan and at Selete, an R&D organization. ASML and Nikon are reportedly supposed to ship full-blown production EUV tools this year or next.
Still, the clock is ticking for EUV. EUV is a next-generation lithography (NGL) technology that was supposed to be inserted for production at the 65-nm node. But the technology has been delayed, due to the lack of power sources, defect free masks, resists and metrology infrastructure.
Still, leading-edge chip makers are banking on EUV for production fabs, in an effort to avoid the dreaded and costly double-patterning era for optical lithography. But chip makers have no choice but to go to double patterning. Experts believe that EUV is now targeted for production at the 16-nm node-or later.
At Intel, the company used dry 193-nm lithography at the 45-nm node. Then, at 32-nm, it inserted its first 193-nm immersion tools for production, mainly from Nikon.
At 22-nm, Intel will continue to use 193-nm immersion lithography. The chip giant is expected to use both ASML and Nikon for the critical layers for its 22-nm node, which will go into production in the second half of 2011.
Then, at 14-nm, the chip maker will continue to use 193-nm immersion, plus a double-patterning technique called pitch splitting. In some conferences, Intel has talked about using quintuple patterning at 14-nm. The company hopes to set up an EUV pilot line for the 14-nm node, but it’s unclear if EUV will be ready in time.
In any case, Intel has already defined and finalized its design rules for the 14-nm node-some two years before the devices move into production. The design rules for 14-nm are ”frozen,’’ Sivakumar said.
At 65-nm and above, Intel used 2-D random and complex layouts in chip design. Scaling 2-D random layouts are difficult at 45-nm. So, starting at 45-nm, Intel moved towards 1-D unidirectional, gridded design rules, he said.
For the 10-nm node, Intel hopes to use 193-nm immersion for the non-critical layers and EUV for the more complex and finer line cut steps. ”EUV is our primary option’’ in those steps, he said. If EUV is not ready, Intel may use maskless or 193-nm immersion to handle the line cut steps.
In any case, Intel has already defined its design rules for 10-nm, which will be based on a 1-D unidirectional, gridded scheme. But here’s the dilemma: Intel’s 10-nm design rules must adhere to either an EUV-centric world or a 193-nm immersion scheme-not both, he said.
EUV is late for the design rule definition stage for Intel’s 10-nm node, he said. Intel has reportedly started to devise its design rules based on 193-nm immersion and a multiple-patterning scheme.
When the EUV tools are ready, Intel could backtrack and re-define the design rules. So, in effect, there is still time for EUV to be inserted at the 10-nm node, he said. If the tools are not ready, Intel must look at other options. The company’s 10-nm design rules will be officially frozen in the first quarter of 2013.
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