Intel invests $3.5 billion in chiplet packaging

Intel invests $3.5 billion in chiplet packaging

Business news |
By Peter Clarke

The multiyear investment will make Rio Rancho a center of excellence for chiplet-style manufacturing and is expected to create 700 jobs over the next three years as well as 1,000 construction jobs in the short term. Construction is expected to start late in 2021.

Foveros, introduced in 2019, is Intel’s approach towards chiplet style manufacturing of components. It allows 3D face-to-face die stacking. A base logic die can have one more active die on top, such as another logic die, memory, an FPGA or analog/RF.

Intel is taking a similar path to leading foundry TSMC which announced in June 2020 that it would spend $10 billion on an IC assembly, packing and test facility in Miaoli, northern Taiwan (see Chiplet-savvy TSMC to build $10 billion assembly and test plant).

“A key differentiator for our IDM 2.0 strategy is our unquestioned leadership in advanced packaging, which allows us to mix and match compute tiles to deliver the best products,” said Keyvan Esfarjani, the general manager of Intel’s manufacturing and operations, in a statement. “We’re seeing tremendous interest in these capabilities from the industry, especially following the introduction of our new Intel Foundry Services.”

Related links and articles:

News articles:

Chiplet-savvy TSMC to build $10 billion assembly and test plant

TSMC preps for ‘chiplet’ style manufacturing in 2021

Report: TSMC, Japan to share cost of Tokyo chip facility

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles