Intel joins open-source hardware group, donates AIB bus
Intel has made use of the AIB within its own multi-die components.
The CHIPS Alliance was founded in 2019 by the Linux Foundation with a charter to host and curate high-quality open source code relevant to the design of silicon devices (see Linux meet RISC-V: open source groups team up). Early backers include Esperanto Technologies, Google, SiFive and Western Digital who have been joined by Alibaba, Samsung, Futurewei (Hauwei’s US research arm) and Imperas amongst others.
The CHIPS Alliance project develops and hosts open source register transfer level (RTL) code and software development tools for the design of open source CPUs, SoCs, interconnect IP and peripherals for FPGAs and custom silicon. These open-source IP cores are intended for use in consumer and mobile electronics, computing and Internet of Things (IoT) applications.
Intel will share its Advanced Interface Bus (AIB) as an open-source, royalty-free PHY-level standard for connecting multiple semiconductor die within the same package.
This effort is intended to encourage an industry environment in which silicon IP can be developed using any semiconductor process as a “chiplet,” and integrated with other chiplets into a single component. Broader adoption and support for AIB-enabled chiplets will help device developers grow beyond the limits of traditional monolithic semiconductor manufacturing and reduce the cost of development. The CHIPS Alliance said Intel’s donation would help grow a chiplet ecosystem and support more device innovation via heterogeneous integration.
The AIB specifications and other materials will be further developed in the Interconnects workgroup of the CHIPS Alliance and be placed in the CHIPS Alliance github.
Intel is joining CHIPS Alliance organization at its highest “platinum” level, alongside Alibaba, Google, SiFive and Western Digital. This gives the company a seat on the governing board. Zvonimir Bandić, is chairman of CHIPS Alliance, and senior director of next-generation platforms architecture at Western Digital.
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