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Intel looks to 1nm for trillion transistor ‘chips’

Technology News |
By Nick Flaherty


Intel has detailed three areas of research that will put a trillion transistors into a package.

Pat Gelsinger, CEO of Intel, highlighted this strategy back in August, and the company is showing some of the supporting research at the IEEE International Electron Devices Meeting (IEDM) in the US this week.  

The research has a number of strands, from chiplet 3D packaging technology that gives a 10x improvement in density as well as 2D materials for 1nm transistors beyond RibbonFET that are just 3 atoms thick and new stackable ferroelectric memories.

Intel needs to compete in the technology roadmap against TSMC and Samsung for the fledgling Intel Foundry Service (IFS) as both have plans to 1nm.

“Seventy-five years since the invention of the transistor, innovation driving Moore’s Law continues to address the world’s exponentially increasing demand for computing. At IEDM 2022, Intel is showcasing both the forward-thinking and concrete research advancements needed to break through current and future barriers, deliver to this insatiable demand, and keep Moore’s Law alive and well for years to come,” said Gary Patton, Intel vice president and general manager of Components Research and Design Enablement.

The first area is in heterogeneous 3D packaging, or chiplets, that Intel calls ‘quasi-monolithic chips’. Here Intel says it has developed a 3 um pitch for hybrid bonding, down from the current 10um pitch.

Intel also demonstrated a gate-all-around stacked nanosheet structure using 2D channel material just 3 atoms thick, while achieving near-ideal switching of transistors on a double-gate structure at room temperature with low leakage current. These are two key breakthroughs needed for stacking GAA transistors and moving beyond the fundamental limits of silicon, says Patton.

Researchers also discussed a comprehensive analysis of electrical contact topologies to 2D materials that could further pave the way for high-performing and scalable transistor channels.

Intel has also demonstrated stacked ferroelectric capacitors that match the performance of conventional ferroelectric trench capacitors and can be used to build FeRAM on a logic die.

A device-level model captures mixed phases and defects for improved ferroelectric hafnia devices, marking significant progress for Intel in supporting industry tools to develop novel memories and ferroelectric transistors.

www.Intel.com/ProcessInnovation


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