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Intel plans 3nm chiplet for satellite terminal

Technology News |
By Nick Flaherty


Intel is developing 3nm, RF and photonic chiplets for a reconfigurable terminal to connect multiple satellite constellations.

The company is working on the Phase 1 of the Space-Based Adaptive Communications Node (Space-BACN) programme from the US Defense Advanced Research Projects Agency (DARPA).

The terminal, developed over the next three years, will enable communications between satellite constellations in space.

The DARPA programme aims to connect up broadband low earth orbit (LEO) constellations from SpaceX, Amazon’s Kuiper, Telesat and Viasat.

There are three technical areas in the programme.

Technical Area 1 (TA1) focuses on the development of an optical aperture for pointing, acquisition and tracking, as well as the optical transmit and receive functions. This will be developed by CACI, Mbryonics and Mynaric.

This will interface to TA2 a reconfigurable optical modem using both single-mode and polarization maintaining fibre (PMF). This will be built by Intel with II-VI (now Coherent) Aerospace and Defense and Arizona State University to support both current and new communication standards and protocols to enable interoperability among satellite constellations. 

Intel plans to use its Intel3 process technology for a digital signal processor chiplet to handle the forward error correction, as well as a front end chiplet on Intel 16, using FinFET RF transistors for the integration of high-speed data converters, transimpedance amplifier (TIAs) and drivers.

A photonic chiplet will be built with process technology from Tower Semiconductor in Israel, which is being acquired by Intel. This offers low-loss waveguides and options, such as V-groove, enabling automated high-volume fibre coupling integration and assembly.

These will be integrated on an Intel Agilex FPGA as a substrate using Intel’s embedded multi-die interconnect bridge (EMIB) and advanced interface bus (AIB) packaging technologies into a single multi-chip package (MCP).

Chiplets are key to Intel’s growth strategy to combine different technologies for large devices in a single package says Intel CEO Pat Gelsinger (above). The DARPA project is a good way to shakeout problems with the integration of multiple technologies in a low volume, high performance design. 

“Intel’s vision is to create world-changing technology that improves the life of every person on the planet. This program helps us to deliver on that vision by enabling global connectivity from space to anywhere across the planet – enabling broadband services and the IoT where not just every person but everything is connected,” said Sergey Shumarayev, Intel senior principal engineer and principal investigator in the Programmable Solutions CTO Group.

The third Technical Area 3 (TA3) will see the constellation providers identify critical command and control elements required to support cross-constellation optical intersatellite link communications and develop the schema necessary to interface between Space-BACN and commercial partner constellations.

Intel has started Phase 1 of the program with the design each of the above chiplets and is working with the other performers to fully define the interfaces between the system components in each of the other technical areas. This phase will last 14 months and conclude with a preliminary design review.

At the completion of Phase 1, selected performers in the first two technical areas will participate in an 18-month Phase 2 to develop engineering design units of the optical terminal components, while performers in the third technical area will continue to evolve the schema to function in more challenging and dynamic scenarios.

www.intel.com

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