Intel prepares for trillion transistor era shake up

Intel prepares for trillion transistor era shake up

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By Nick Flaherty

Chip makers will be able to put a trillion transistors in a package by the end of the decade in a move that will shake up the industry, says Pat Gelsinger, CEO of Intel.

This is one of the key drivers for Intel’s move into offering foundry services, he told leading chip designers in a keynote for the HotChips 34 conference in California last night. This will lead to more sharing of IP and drive new EDA tools, he says.

“We see our way clear to getting to a trillion transistors by the end of the decade,” he said. “With Ribbon FETs, using topside signal and backside power distribution and EUV and high NA we have a good path to the end of the decade,” he said, “With 2.5 and 3D packaging, these four together give us a path to a trillion transistor by the end of the decade.”

He points to Intel’s Ponte Vecchio chip, discussed at the conference, which already has 100bn transistors, built with chiplets, or ‘tiles’ in multiple process technologies on a substrate. This technique is also being used for the Meteor Lake processors that will combine chips built by Intel and TSMC in a single package.

He believes Intel is back on track with the process technology with the Intel 4 being comparable to leading edge processes today.

“We will have the Intel 18A process in late 2024 [with RibbonFETs and backside power delivery] which we expect to be best in class, and we have the nodes lined up for the rest of the decade, also with the power delivery, that’s the core limiter. We feel pretty comfortable with that path,” he said.

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The UCIe standard announced recently is key to this development, he says, which creates more of  system foundry than a chip foundry. He points to Intel being a key driver of the USB and PCI Express standards, and now UCIe, which the company plans to use in its devices going forwards. “We are pretty excited about the next phase of an open system foundry,” he said “The system problems of today will become the chiplet problems of tomorrow.”

However UCIe may co-exist with other protocols such as AMR’s AXI. “There are going to lower power standards and custom versions for higher end designs, so there will be a certain amount of gestation as the industry decides on the right partition for the chiplet architectures,” he said.

“Software is a critical element of a systems foundry,” he said, pointing to Intel’s development of Oneapi to give the same API for GP, AI and CPU developers, as well as its Simics system simulation tool.

This will also need new design tools.

“We are going to need the next generation of EDA tools, now its going to have to synthesize this hardware system and software across multiple domains so that will be a whole new class of EDA tools to tackle these system problems at scale,” he said. “All of a sudden you will see the industry reforming. What is a CPU in the future, its not clear any more, we will have systems with CPUs, GPUs and IPU (interface units),” he said.

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“Our foundry customers will have access to the libraries of IP including software, some will be hard IP, some soft IP, some chiplets, as well as 3rd party IP providers such as Synopsys and ARM. “Someone like Nvidia will be able to use Intel product group blocks, they are using Sapphire Rapid processor now and they might be able to buy in those as chiplets. They could do that in the PCIe world at the board level, now they can do that in the systems foundry level in the chiplet package level.”

“There’s never been a better time to be in the silicon industry,” he said.;

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