Intel pushes 10-nanometer volume production back to 2019

Intel pushes 10-nanometer volume production back to 2019

Technology News |
By eeNews Europe

“We are shipping in low volume and yields are improving, though the rate of improvement is slower than we anticipated,” said Brian Krzanich, Intel’s chief executive, in a conference call with financial analysts. “We understand the yield issues and have defined improvements for them, but they will take time to implement and qualify.”

Intel became the world’s largest maker of computer processors by following the tenets of Moore’s Law, which says that the number of transistors that can be placed on a single silicon chip doubles roughly every two years. But the company has fallen behind the prescribed pace, with every new generation of chips separated by about three years.

(Image courtesy of Intel).

The 10nm problems are the latest setback for the Santa Clara, California-based company, which has long used manufacturing prowess to stay ahead of rivals like Taiwan Semiconductor Manufacturing Corporation. Intel had said it would deliver the 10nm process in the first half of 2016, but it continues to extend the due date.

Under pressure from customers and investors, Intel has also been forced to update its tick-tock development model. For almost a decade, it has followed up every new process technology with a new processor architecture, which is reflected by an “+” in the node name. But in 2016, Intel added another step to the model, in which it optimizes the architecture.

Currently, Intel makes chips based on 14nm+ technology. But in the second half of the year, the company plans to release two new lines of chips likely based on 14nm++ technology. The product lines are Whiskey Lake for personal computers and Cascade Lake for data centers. That technology will provide 70 percent more performance than the original 14nm process.

“If anybody else had 70 percent improvement on a technology node, they might just rename the node,” Krzanich said on the conference call. “And we have always chosen to be really transparent and just say, it is an improvement on an existing technology, rather than renaming [the node].”

Manufacturing issues stand in the way of the Intel’s next generation of chips. Intel still employs a technology called deep ultraviolet lithography, which shoots intense beams of light onto silicon wafers, etching patterns where the light touches down. To produce smaller transistors, it uses a technique called multi-patterning, which adds several steps to the process, raising the risk of defects.

The more defects there are on silicon wafers, the lower the yield. Intel needs to eliminate the errors to keep manufacturing costs in check. This is the company’s last generation of chips before it shifts to extreme ultraviolet (EUV) lithography, which can condense the number of patterning steps by using smaller wavelengths of light.

In the meantime, competitors are nipping at Intel’s heels. The two largest foundries in the world, TSMC and GlobalFoundries, both recently started volume production of chips based on 7nm processes. And analysts say that technology could compete closely with Intel’s 10nm technology, which is speedier but likely costs slightly more per transistor. Samsung is also working on 7nm manufacturing.

“As Intel’s 10nm process lags further behind schedule, the company’s once formidable manufacturing advantage is disappearing,” Linley Gwennap, principal analyst for The Linley Group, wrote in a recent newsletter. “Intel can no longer count on superior manufacturing technology to give its products an edge in the market.”

Intel said that its 10nm process can etch 100.8 million transistors onto each square millimeter of silicon, a metric that the company has pushed as a potential new benchmark for the semiconductor industry. New benchmarks are probably needed because node names no longer line up with transistors features.

Intel has been trying to offset the end of Moore’s Law with advances in transistor density. The transistors inside Intel’s 14nm chips can be packed 2.4 times tighter than they can inside Intel’s previous generation of chips based on the 20nm process. The company is aiming to aggressively boost the transistor density another 2.7 times with its 10nm node, Krzanich said.

“We think we bit off a little too much in this case,” he said.

This article first appeared on Electronic Design –

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