eASICs is a 19-year old company with its own structured ASIC approach based on the use of a programmable silicon vias rather than the SRAM-based routing used in conventional FPGAs. The result means that die sizes can be reduced in compared to equivalent functionality FPGAs and cost and power saved, the company claims.
Intel did not disclose how much it is spending to acquire eASICs, which will join Intel’s Programmable Solutions Group that was formed when Intel acquired Altera Corp. for $16.7 billion at the end of 2015.
A structured ASIC is an intermediary technology between FPGAs and ASICs. It offers performance and power-efficiency closer to a standard-cell ASIC, but with the faster design time and at a fraction of the non-recurring engineering costs associated with ASICs.
“Specifically, having a structured ASICs offering will help us better address high-performance and power-constrained applications that we see many of our customers challenged with in market segments like 4G and 5G wireless, networking and IoT. We can also provide a low-cost, automated conversion process from FPGAs, including competing FPGAs, to structured ASICs,” said Dan McNamara, general manager of the programmable solutions group at Intel, in a statement. “Longer term, we see an opportunity to architect a new class of programmable chip that takes advantage of Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology to combine Intel FPGAs with structured ASICs in a system in package solution.”
The deal is expected to close in 3Q18 after customary conditions are met.
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