Intel shows engineering silicon of its biggest ever ‘chip’

Intel shows engineering silicon of its biggest ever ‘chip’
Technology News |
Intel has seen first silicon of one of the most complex chips it has ever made, the 100bn transistor Ponte Vecchio discrete graphics processor for high performance computing and AI acceleration
By Nick Flaherty


Intel has built a device with over 100bn transistors for the data centre and supercomputers using a combination of its own Intel 7 process and TSMC N5 5nm. 

“Ponte Vecchio is our tour-de-force data centre GPU architecture with Intel’s highest ever compute density. Looking back at just the past year, technology was at the heart of how we all communicated, worked, played and coped through the pandemic. Enormous computing power proved crucial. Looking ahead, we face a massive demand for compute – potentially a 1,000x need by 2025. That 1,000-times boost in four years is Moore’s Law to the power of five,” said Raja Koduri, Senior vice president and General manager of the Accelerated Computing Systems and Graphics Group.

“This is the most complex SoC Intel has ever built and a great example of our IDM 2.0 strategy come to life,” he said. “With this product, we are bringing to life our moon-shot project, the 100 billion-transistor device that delivers industry-leading FLOPs and compute density to accelerate artificial intelligence, high performance computing and advanced analytics workloads.”

There is a discussion on the transistor density for Moore’s Law, based on Intel’s roadmap, at How long has the semiconductor industry got?

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Ponte Vecchio takes advantage of several advanced semiconductor processes by using the EMIB technology and Foveros 3D packaging as well as the 5nm process at TSMC. Embedded Multi-die Interconnect Bridge (EMIB) uses a very small bridge die, with multiple routing layers, embedded as part of our substrate fabrication process. All of this creates the 100bn transistors in the system-in-package, rather than a monolithic die.

Ponte Vecchio is comprised of several complex designs that are built on separate tiles and then assembled through an EMIB tile that enables a low-power, high-speed connection between the tiles. These are put together in Foveros packaging that creates the 3D stacking of active silicon for power and interconnect density. A high-speed MDFI interconnect allows scaling from one to two stacks.

The Compute Tile is a dense package of Xe -cores and is the heart of Ponte Vecchio. One tile has eight Xe -cores with a total of 4MB L1 cache for power-efficient compute. The tile has an extremely tight 36-micron bump pitch for 3D stacking with Foveros and is buil ton the TSMC N5 5nm process.

The Base Tile is the connective element of Ponte Vecchio. It is a large die built on the Intel 7 (10nm) optimized for Foveros technology. This integrates all the complex I/O and high bandwidth components come together with the SoC infrastructure for PCIe Gen5, HBM2e memory, MDFI links to connect tile-to-tile and EMIB bridges.

The Link Tile provides the connectivity between GPUs supporting eight links per tile which is critical for scale-up for HPC and AI. This is targeting 90G SerDes to enable the scale-up solution for the Aurora exascale supercomputer

Tests of the initial A0 engineering silicon is showing 45 TFLOPS FP32 performance for AI with 5 TBps Memory Fabric bandwidth and greater than 2 TBps connectivity bandwidth.

This will use the Intel’s oneAPI open, standards-based, cross-architecture and cross-vendor unified software stack that is also used for the Xe HPG and Alchemist discrete GPUs that will be coming to market in the first quarter of 2022 for high end gaming under the newly announced  Arc brand. The Ponte Vecchio chip is yet is not under the Arc brand but is in validation and has begun limited sampling to customers. Ponte Vecchio will be released in 2022 for HPC and AI market.

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