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Intel tips glass substrate for chiplet packaging

Intel tips glass substrate for chiplet packaging

Technology News |
By Peter Clarke



Intel has started producing test examples of glass substrates for chiplet packaging.

For its glass substrates Intel uses the same 510mm by 515mm panel size that it already uses for organic substrates. These are then diced to the appropriate size to hold multiple chiplets for multidie packaging.

The company said that glass offers better flatness and thermal and mechanical stability compared with organic insulator substrates.

Glass substrates can tolerate higher temperatures, offer 50 percent less pattern distortion, and have ultra-low flatness for improved depth of focus for lithography, and have the dimensional stability needed for extremely tight layer-to-layer interconnect overlay. As a result of these distinctive properties, a 10x increase in interconnect density is possible on glass substrates. Further, improved mechanical properties of glass enable large form-factor packages with high assembly yields.

A photo shows the multi die assembly side of an Intel assembled glass substrate test chip at Intel’s Assembly and Test Technology Development factories in Chandler, Arizona, in July 2023. Intel’s advanced packaging technologies come to life at the company’s Assembly and Test Technology Development factories. Source: Intel.

Intel said it hoped to be able to integrate a trillion transistors within a single component package by 2030.

The glass-based technology is likely to come into use in the second-half of the decade Intel said where it will be used in high-value applications with workloads requiring larger form factor packages – such as data centers, AI, graphics – and higher speed capabilities.

“After a decade of research, Intel has achieved industry-leading glass substrates for advanced packaging. We look forward to delivering these cutting-edge technologies that will benefit our key players and foundry customers for decades to come,” said Babak Sabi, senior vice president and general manager of Assembly and Test Development at Intel.

A photo shows the ball grid array side of an Intel assembled glass substrate test chip at Intel’s Assembly and Test Technology Development factories in Chandler, Arizona, in July 2023. Intel’s advanced packaging technologies come to life at the company’s Assembly and Test Technology Development factories. Source: Intel.

As product roll out reduces the unit cost the same technology is expected to migrate into other applications such as processors for laptop computers and smartphones.

Related links and articles:

www.intel.com

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