Intel to add AI to Altera Quartus FPGA tool

Intel to add AI to Altera Quartus FPGA tool

Business news |
By Nick Flaherty

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Intel is adding AI support to its Quartus FPGA tools as it spins off the business as Altera.

“As customers deal with increasingly complex technological challenges and work to differentiate themselves from their competitors and accelerate time to value, we have an opportunity to reinvigorate the FPGA market,” said Sandra Rivera, chief executive officer of Altera, which Intel is looking to spin out in the next couple of years.

Quartus was developed by Altera to address the complexity in FPGA design and added DSP capability back in 2014 before the acquisition by Intel. Intel is adding ‘easy-to-incorporate’ AI capabilities to capitalize on the fast-growing AI market particularly for the Agilex 5 which have DSP blocks enhanced to support AI Tensor calculations.

The Quartus update includes the FPGA AI Suite and OpenVINO, which generate optimized intellectual property (IP) based on standard frameworks like TensorFlow and Pytorch.

Intel plans to IPO its FPGA business

The Agilex 5 FPGAs are built in a 7nm process and are now in mass production. This is also the first ‘asymmetric’ applications processor system with dual-core ARM Cortex-A76 and a dual-core ARM Cortex-A55 processors on the monolithic die. This is in contrast to the AMD/Xilinx FPGAs which use separate AI accelerator chiplets.

The Agilex 5 includes high-speed GTS transceivers up to 28.1 Gbit/s and PCI Express 4.0 ×8 support as well as DDR5 external memory interface up to 4,000 Mbit/s.

The Agilex 9 FPGAs are also now in volume production with high speed data converters for radar and military-aerospace applications that require high-bandwidth mixed-signal FPGAs.

The Agilex 7 F-series and I-series devices are released to production to boost the fabric performance per watt for data centre, networking and defence applications. These use the R-Tile chiplet to add PCIe 5.0 and CXL capabilities and the only FPGA with hard intellectual property (IP) supporting these interfaces.

Agilex 3 is planned as a low-power, value line of FPGAs to low-complexity functions for cloud, communications and intelligent edge applications.


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