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Intel, TSMC to detail 2nm processes at IEDM

Intel, TSMC to detail 2nm processes at IEDM

Technology News |
By Peter Clarke

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Intel’s attempts to get back to the leading-edge in chipmaking and foundry TSMC’s steps defining that leading-edge will be on show at this year’s International Electron Devices Meeting (IEDM) coming up in December, in San Francisco.

In a late news paper, researchers from TSMC will unveil the N2 manufacturing process, which is a nominal 2nm process designed for computing in AI, mobile and high-performance computing. In the following paper in the same session Intel engineers will provide details of scaling RibbonFETs, the name Intel gives to its nanosheet transistors.

At the IEDM conference TSMC researchers are expected to report that N2 offers a 15 percent speed gain or 30 percent power reduction at a chip density improved by 15 percent or better compared to its own N3 (3nm nominal) process introduced in 2022.

Cross-section of N2 interconnect stack showing copper redistribution layer. Source: IEDM and T the cross-sectional image shows that the N2 platform’s Cu redistribution layer (RDL) and passivation provide seamless integration with 3D technologies.

Paper 2.1 2nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications, authored by  G. Yeap et al. from TSMC  is also set to show an SRAM macro with a world-record density of 38Mbits per square millimeter.

The paper will also detail middle- (MEOL) and back-end-of-line (BEOL) interconnect that features a scalable copper-based redistribution layer for flexible placement of input/output pads with reduced barrier resistance); a flat passivation layer (for increased reliability); and through-silicon vias, or TSVs (for interconnecting devices in different layers).

The researchers say the N2 platform has met wafer-level reliability requirements and initial qualification tests. Full qualification is expected in 2025 and mass production in 2026.

Intel

In paper 2.2 Silicon RibbonFET CMOS at 6nm Gate Length,” A. Agrawal et al from Intel are set to show how they build nanosheet technology (RibbonFETs) with 6nm gates and 45nm contacted polysilicon pitch (CPP, the spacing between transistor gates) with no degradation of electron mobility.

Drain-induced barrier lowering (DIBL) versus silicon thickness (Tsi) at gate length of 18nm. shows a reduction as Tsi is scaled from 10nm to 1.5nm; however, DIBL reduction saturates at Tsi <4nm. PMOS DIBL is elevated compared to NMOS DIBL at the same Tsi. Also shown are TEM micrographs of a 1NR transistor with various Tsi values down to 1.5nm. Source: IEDM.

The authors do not reference a specific Intel manufacturing process but RibbonFETs are slated to be inserted into production in the 20A process – nominal 20 angstrom or 2nm process. Intel has seemingly opted not to introduce any of its processor products on 20A and instead go directly from its 3nm process to the 18A process, which may be reflected in the authors focus on nanosheet scaling.

The researchers will show that electron mobility doesn’t degrade until a nanosheet silicon thickness of 3nm. Thereafter electron scattering due to surface roughness becomes an issue. In the paper the authors report how short channel control below silicon thickness of 4nm and workfunction engineering allows for low threshold voltages with 3nm as a

Related links and articles:

www.ieee-iedm.org

News articles:

TSMC begins trial 2nm production for Apple, say reports

Intel, TSMC both set to report on stacked CFETs at IEDM

No date given for Samsung to supply Preferred Networks’ 2nm chips

Rapidus breaks ground on 2nm fab, goes on hiring spree

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