The development builds on Intel’s EMIB (embedded multi-die interconnect bridge) and Foveros is the name of Intel’s approach to 3D packaging.
The items revealed at Semicon West are Co-EMIB, Omnidirectional Interconnect (ODI) and MDIO (multi-die interface)
Co-EMIB: This technology allows for the interconnection of two or more Foveros elements with essentially the performance of a single chip. And designers can also connect analog, memory and other tiles with very high bandwidth and at very low power.
ODI: Intel’s new Omni-Directional Interconnect provides flexibility for communication among chiplets in a package. The top chip can communicate horizontally with other chiplets, similar to EMIB. It can also communicate vertically using through-silicon vias (TSVs) to the base die below, similar to Foveros. And ODI leverages large vertical vias to allow power delivery to the top die directly from the package substrate. Much larger than traditional TSVs, the large vias have lower resistance, providing more robust power delivery simultaneously with higher bandwidth and lower latency enabled through stacking. At the same time, this approach reduces the number of TSVs required in the base die, freeing up more area for active transistors and optimizing die size.
MDIO: Building upon its Advanced Interface Bus (AIB) PHY level interconnect, Intel disclosed a die-to-die interface called MDIO. The technology enables a modular approach to system design with a library of chiplet intellectual property blocks. MDIO provides better power efficiency and more than double the pin speed and bandwidth density offered by AIB, Intel stated.
“Intel’s vertically integrated structure provides an advantage in the era of heterogeneous integration, giving us an unmatched ability to co-optimize architecture, process and packaging to deliver leadership products,” said Babak Sabi, Intel corporate vice president for assembly and test technology development, in a statement.