Intel’s backside power prominent at VLSI Symposium

Intel’s backside power prominent at VLSI Symposium

Technology News |
By Peter Clarke

Backside power distribution is well-represented at the upcoming 2023 Symposium on VLSI Technology and Circuits with papers from Intel, IMEC and Samsung. The conference is due to take place in Kyoto, Japan, June 11 to 16.

The idea of using the backside of silicon die for power rails with through-silicon vias (TSVs) to take power up to surface diffused circuits was introduced by the IMEC research institute in 2019. It is now starting to be implemented in commercial manufacturing processes and has been adopted by Intel under the name PowerVia for the Intel 4 process due to arrive in 2024.

At the conference Intel engineers are due to report on the implementation of its E-Core processor using PowerVia. “E-Core Implementation in Intel 4 with PowerVia (Backside Power) Technology” – Intel Corp. (Paper T1-1).

 An E-core is an x86 processor core optimized for energy consumption rather than performance. The use of PowerVia enables standard cell utilization exceeding 90 percent in large areas of the core while showing more than 5 percent frequency benefit in silicon due to reduced IR drop. Post-silicon debug is demonstrated with slightly higher throughput times.

In a second paper – Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing” – Intel Corp. (Paper T6-1) – Intel researchers discuss the use of PowerVia on Intel-4 for high-performance computing. The claim is made that “PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing.” A fabricated Atom core with greater than 90 percent cell utilization showed greater than 30 percent platform voltage droop improvement and 6 percent frequency benefit compared to a similar design without PowerVia.

A backside session

Later in the program backside power delivery networks (BSPDNs) are the subject of a complete session. Here, in paper TFS2-1, Intel presents an experimental demonstration of a novel cell architecture with back-side device contacts and back side power delivery.

IMEC, the original proponent of BSPDNs, is scheduled to discuss possible integration flows and challenges associated with integrating a great many nano-TSVs. There are complexities here related to option and extent of the use of power rail integration schemes. These can be buried in the shallow trench isolation and the silicon below the devices or directly integrated as a complete backside metallization scheme on the wafer backside. The technology challenges include the extreme wafer thinning required and back-side lithography correction needed to compensate for wafer distortions caused by wafer processing and wafer-to-wafer bonding.

Samsung’s take

Samsung, set to introduce BSPDN with its 2nm manufacturing process in 2025, will provide a simulation of stress concentrations due to the use of a both-side backend-of-the-line (BEOL) structure. Samsung’s conclusion is that there are increased risks of delamination in certain metal layers and this brings implications for optimizing the dimensions of micro TSVs, the materials used and ring-oscillator performance.

 A joint paper from IMEC and Arm in this session evaluates the impact of backside power delivery on the implantation of a commercial 64-bit processor block at the A14 (14 angstrom) or 1.4nm) node. A backside BEOL, including nTSV connections, is proposed and calibrated using TCAD and experimental data. The developed stack is modelled in a commercial cell-level parasitic extraction tool to enable its use during place and route. The same benchmark is physically implemented using imec’s own A14 PDK.

The authors will report that the backside PDN enables a core area reduction from 8 to 23 percent, which in turn produces a 2 to 6 percent improvement in frequency compared to the frontside PDN.

Related links and articles:

News articles:

IEDM papers present FDSOI for quantum computing

Stacked CMOS could overcome Forksheet limitations, says IMEC

Intel catching up with TSMC?

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